Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.2.5 Outbound Read TransactionAn outbound read transaction is initiated by the Intel ® 80200 processor and is targeted at a PCIslave on either the primary or secondary PCI buses. The read transaction is propagated through theoutbound transaction queue (OTQ) and read data is returned through the outbound read queue(ORQ).The ATUs internal bus slave interface claims the read transaction and forwards the read requestthrough to the PCI bus and returns the read data to the internal bus. The byte enables for the firstword only of the transaction are also passed by the ATU (to cover the case of less than 1 Dwordbeing requested). The fetch data amount used by the PCI side is determined by the read commandused on the internal bus by the IB master. Table 5-2 are the fetch data sizes used during outboundATU read transactions:Table 5-2.Outbound Read Fetch SizesInternal Bus CommandOutbound Fetch SizeMemory ReadMemory Read LineMemory Read Multiple4 Bytes (1 Dword)8 Bytes (2 Dwords)16 Bytes (4 Dwords)The data flow for an outbound read transaction on the local bus is summarized in the followingstatements:• The ATU internal bus interface latches the internal bus address when the address is inside anoutbound address translation window (or the direct addressing window, when enabled) and theOTQ is empty. When the OTQ is not empty (previous outbound transaction in progress), theinternal bus interface signals a Retry to the transaction initiator.• Once the outbound internal address is latched into the OTQ, a Retry is signaled to the internalbus master and a delayed read transaction is initiated. The ATU signals the CIU at the time ofthe Retry that a delayed cycle has started and that it should not request the internal bus until theATU has notified it that the data to be read is now available.• If during the completion cycle on the PCI interface, a master abort is encountered, a flag is setand the ATU notifies the CIU that it may now request the internal bus to complete the retriedtransaction. A master abort condition is returned once the IB master has acquired the bus andasserted the address of the delayed read completion cycle. The OTQ is cleared of thetransaction.• Once the transaction completes on the PCI bus, the ATU notifies the CIU that it may nowrequest the internal bus to complete the retried transaction. The outbound read wasdeterministic with no prefetching and data read is the data that was required per the commandused on the internal bus (see Table 5-2).• A target abort encountered on the PCI bus is returned as a target abort to the IB master on thefirst data phase. If a data parity error is signaled on PCI, the bad data is still passed through tothe IB master.Developer’s Manual 5-21