Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.6.5 SERR# Assertion and DetectionThe primary and secondary ATUs are capable of reporting error conditions through the use of theP_SERR# output and the S_SERR# output respectively.The following conditions may result in the assertion of P_SERR# by the primary ATU:• An address parity error is detected by the PATU PCI interface and the Parity Error Responsebit and the P_SERR# Enable aresetinthePATUCMD.• An inbound write transaction is target aborted when the transaction is attempted on the internalbus, the Primary ATU Inbound Error P_SERR# Enable bit in the PATUIMR is set by the memorycontroller, and the P_SERR# Enable bit is set in the PATUCMD.• An inbound write transaction is master aborted on the internal bus, the Primary ATU InboundError P_SERR# Enable bit in the PATUIMR is set, and the P_SERR# Enable bit is set in thePATUCMD.• The P_SERR# Manual Assertion bit in the ATUCR has been set by the Intel ® 80200 processor andthe P_SERR# Enable bit is set in the PATUCMD.The following conditions may result in the assertion S_SERR# by the secondary ATU:• An address parity error is detected by the SATU PCI interface and the Parity Error ResponsebitandtheS_SERR#EnablearesetintheSATUCMD.• An inbound write transaction is target aborted by the memory controller when the transactionis attempted on the internal bus, the Secondary ATU Inbound Error S_SERR# Enable bit in theSATUIMR is set, and the S_SERR# Enable bit is set in the SATUCMD.• An inbound write transaction is master aborted on the internal bus, the Secondary ATUInbound Error S_SERR# Enable bit in the SATUIMR is set, and the S_SERR# Enable bit is setin the SATUCMD.• The S_SERR# Manual Assertion bit in the ATUCR has been set by the Intel ® 80200 processorand the S_SERR# Enable bit is set in the SATUCMD.Note that the SERR# manual assertion bits must be cleared manually before they can be set againresulting in SERR# asserted. Refer to Section 5.7.37, “ATU Configuration Register - ATUCR” onpage 5-98 for details. For S_SERR# assertions by the SATU, the bridge must be programmed topass the error upstream for detection by a host processor.The following actions with the given constraints are performed by the primary and secondaryATUs when SERR# is asserted by the PCI interface:Table 5-16.SERR# Assertion on the Primary and Secondary ATUsPrimary ATUSet the P_SERR# Asserted bit in the PATUSRIf the PATU P_SERR# Asserted Interrupt Mask bit inthe PATUIMR is clear, set the P_SERR# Asserted bitinthePATUISR.Ifset,noactionIf the PATU P_SERR# Detected Interrupt Mask bit inthe ATUCR is clear, set the P_SERR# Detected bit inthePATUISR.Ifset,noactionSecondary ATUSet the S_SERR# Asserted bit in the SATUSRIf the SATU S_SERR# Asserted Interrupt Mask bit inthe SATUIMR is clear, set the S_SERR# Asserted bitintheSATUISR.Ifset,noactionIf the SATU S_SERR# Detected Interrupt Mask bit inthe ATUCR is clear, set the S_SERR# Detected bit intheSATUISR.Ifset,noaction5-46 Developer’s Manual