Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.4.5 Private Type 0 Commands on the Secondary InterfaceType 0 configuration read and write commands can be generated by the Secondary AddressTranslation Unit of the Intel ® 80312 I/O companion chip. These Type 0 configuration commandsare required to configure private PCI devices on the Secondary bus which are in private PCIaddress space. These commands are initiated by the Address Translation Unit and not by Type 1commands on the Primary bus. Any device mapped into this private address space is not part of thestandard Secondary PCI address space and therefore is not configured by the system hostprocessor. These devices are hidden from PCI configuration software, but are accessible from theIntel ® 80312 I/O companion chip Secondary Address Translation Unit. See Chapter 5, “PCIAddress Translation Unit” for complete description of private PCI address space implementation.In Type 0 Secondary interface commands, S_AD[31:11] are used to select the target device IDSELinput. In Type 1 to Type 0 conversions, P_AD[15:11] are decoded to assert a unique address linefrom S_AD[31:16] on the Secondary interface as described in Section 4.4.2, “Type 1 Commandsand Type 1 to Type 0 Conversions” on page 4-9. This leaves S_AD[15:11] on the Secondaryinterface open for a possibility of up to 5 address lines for IDSEL assertion of private PCI devices.These 5 address lines shall be reserved for private PCI devices on the Secondary PCI bus.When more than five unique address lines are required, the Secondary IDSEL Select Register(SISR) can be programmed to block an additional 10 address lines during Type 1 to Type 0conversions from the Primary interface. Secondary addresses S_AD[25:16] are the addresses thatcan be masked by the SISR register. By setting bits 0 through 9 (corresponding to S_AD[25] -S_AD[16]) in the SISR, the associated address line can be forced to remain deasserted for theP_AD[15:11] encodings of 00000 2 - 01001 2 and therefore are free to be used as an IDSEL selectline for private Secondary PCI devices. Table 4-4 shows the possible configurations ofS_AD[31:11] for public/private Type 0 commands on the Secondary interface. For example, whenSISR Bit 9 is set, S_AD[16] will never be asserted during a Type 1 to Type 0 conversion from thePrimaryPCIbus.ItcanonlybeassertedbytheSecondaryAddressTranslationUnit.When Primary interface receives a Type 1 command that intends to use an S_AD address linesreserved for private PCI devices, the bridge will perform the Type 1 to Type 0 conversion but notassert the reserved S_AD address line. The Type 0 command will then be ignored on the SecondaryPCI bus.By using the SISR register and the five reserved address lines, a total of 15 IDSEL signals areavailable for private PCI devices.Table 4-4.Public/Private PCI Memory IDSEL Select ConfigurationsPrimaryAddressP_AD[15:11]Secondary AddressesS_AD[31:11] withAll SISR Bits = 0Secondary IDSEL SelectRegisterBits 9-0Secondary AddressesS_AD[31:11] withSISR Bits Programmed00000 0000 0000 0000 0001 0000 0 2 1XXXXXXXXX 2 0000 0000 0000 0000 0000 0 200001 0000 0000 0000 0010 0000 0 2 X1XXXXXXXX 2 0000 0000 0000 0000 0000 0 200010 0000 0000 0000 0100 0000 0 2 XX1XXXXXXX 2 0000 0000 0000 0000 0000 0 200011 0000 0000 0000 1000 0000 0 2 XXX1XXXXXX 2 0000 0000 0000 0000 0000 0 200100 0000 0000 0001 0000 0000 0 2 XXXX1XXXXX 2 0000 0000 0000 0000 0000 0 200101 0000 0000 0010 0000 0000 0 2 XXXXX1XXXX 2 0000 0000 0000 0000 0000 0 200110 000000000100000000000 2 XXXXXX1XXX 2 0000 0000 0000 0000 0000 0 200111 0000 0000 1000 0000 0000 0 2 XXXXXXX1XX 2 0000 0000 0000 0000 0000 0 201000 2 0000 0001 0000 0000 0000 0 2 XXXXXXXX1X 2 0000 0000 0000 0000 0000 0 201001 2 0000 0010 0000 0000 0000 0 2 XXXXXXXXX1 2 0000 0000 0000 0000 0000 0 2X=Don’t CareDeveloper’s Manual 4-13