Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.6.15 Memory Controller Interrupt Status Register - MCISRSetting the MCISR asserts an IRQ# interrupt to the Intel ® 80200 processor. Upon an interrupt, theIntel ® 80200 processor polls the interrupt status register for each unit. The interrupt status registertells the Intel ® 80200 processor the reason for the interrupt. The MCU has three interruptconditions: first ECC error (MCISR[0]), second ECC error (MCISR[1]), and more than two ECCerrors (MCISR[2]).When the MCU detects an ECC error and both MCISR[0] and MCISR[1] are cleared, the error islogged in ELOG0 and MCISR[0] is set to 1. When one of the MCISR bits are not clear and theMCU detects an error, the error is logged in the unused ELOGx register and the appropriateMCISR bit is set to 1. When both MCISR[0] and MCISR[1] are not clear, any additional ECCerrors are not logged and MCISR[2] is set.Bits 2:0 are read/clear bits which means that to clear them, software must write a one to these bits.Table 3-32.Memory Controller Interrupt Status Register - MCISRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rcPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Processor Local Bus Address1564HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:03 0 Reserved02 0 2both set.0 = No error detectedECC Error N: Indicates that the MCU detected an ECC error while MCISR[1] and MCISR[0] are1 = Error detected01 0 2 0 = No error detectedECC Error 1: Indicates that the MCU detected an ECC error and recorded the error in ELOG1.1 = Error detected and recorded in ELOG100 0 2 0 = No error detectedECC Error 0: Indicates that the MCU detected an ECC error and recorded the error in ELOG0.1 = Error detected and recorded in ELOG03-60 Developer’s Manual