Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitFigure 4-11.Bridge Configuration Header FormatBridge Configuration HeaderPCIAddressOffsetDevice ID Vendor ID 00HPrimary Status Primary Command 04HClass Code Revision ID 08HReservedHeader TypePrimary LatencyTimerCacheline Size0CHReserved10H14HSecondaryLatency TimerSubordinate BusNumberSecondary BusNumberPrimary BusNumber18HSecondary Status I/O Limit I/O Base 1CHMemory Limit Memory Base 20HPCI-to-PCIBridgePrefetchable Memory Limit Prefetchable Memory Base 24H28HReserved2CH30HReservedReservedCapabilities Ptr 34H38HBridge ControlReserved3CHSecondary IDSEL Control Extended Bridge Control 40HPrimary Bridge Interrupt Status44HSecondary Bridge Interrupt Status48HReservedSecondary Arbitration ControlPCI Interrupt Routing ControlSecondary CLKDisableSecondary I/OLimitSecondary I/OBase4CH50H54HIntel® 80312I/Ocompanionchip SpecificSecondary Memory Limit Secondary Memory Base 58HQueue Control Secondary Decode Enable 5CHReserved60HFigure 4-12.Extended Bridge Configuration Header FormatPower Management CapabilitiesReservedPMCSR PCI toPCI Bridge SupportNext Item PointerCapability IdentifierPower Management Control/Status68H6CHDeveloper’s Manual 4-83