Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.11 InterruptsEach channel can generate an interrupt to the Intel ® 80200 processor. The Interrupt Enable bit inthe Descriptor Control Register (DCRx.ie) determines whether the channel generates an interruptupon successful error-free completion of a DMA transfer. Error conditions described inSection 9.12 also generate an interrupt. Each channel has one interrupt output connected to the PCIand Peripheral Interrupt Controller described in Chapter 2, “PCI and Peripheral InterruptController Unit” summarizes the status flags and conditions when interrupts are generated in theChannel Status Register (CSRx).Table 9-2.DMA Interrupt SummaryChannel Status Register (CSR) FlagsInterruptGenerated?InterruptConditionActiveEnd of TransferEnd of ChainPCI Master AbortPCI Target AbortPCI Parity ErrorInternal Bus ErrorDCR.ie SetDCR.ie ClearByte count == 0 &&NDARx != NULL(End of Transfer)Byte Count == 0 &&NDARx == NULL(End of Chain)1 1 0 0 0 0 0 Y N0 0 1 0 0 0 0 Y NPCI Master-Abort 0 0 0 1 0 0 0 Y YPCI Target-Abort 0 0 0 0 1 0 0 Y YPCI Parity Error 0 0 0 0 0 1 0 Y YInternal Bus Error 0 0 0 0 0 0 1 Y YNote:End-of-Transfer and End-of-Chain flags is set only when DCR.ie = 1. When DCR.ie = 0, then theabove flags are always set to 0. End-of-Transfer Interrupt and End-of-Chain Interrupt can only bereported in the CSR when the DMA transfer completed without any reportable errors.The channelshall never report an End-of-Transfer interrupt or End-of-Chain interrupt along with any PCI errorconditions. Multiple error conditions may occur and be reported together. Also, because thechannel does not stop after reporting the End-of- Transfer Interrupt, internal bus errors may occurbefore the End-of-Transfer interrupt is acknowledged and cleared.9-22 Developer’s Manual