Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.3.1 64-Bit ProtocolThe 64-bit PCI extensions have been developed to coincide with the existing 32-bit protocol. Theadditional 32 bits of address/data require an additional four byte enables and a parity signal tocover them. The bus timing, protocol, and turn-around cycles behave exactly the same for the64-bit signals as they do for the standard PCI interface signals with the exception of the 64-bithandshake signals referenced below.The 64-bit handshake signals used by the Intel ® 80312 I/O companion chip are P_REQ64# andP_ACK64# on the Primary interface and S_REQ64# and S_ACK64# on the Secondary interface.As a master, a PCI interface of the bridge will assert REQ64# with FRAME# to indicate to thetarget that a 64-bit transaction is being requested. REQ64# is asserted and deasserted with theexact timing as FRAME# for the master state machines. When REQ64# is asserted, the target ofthe memory operation is required to assert ACK64# with the same timing as DEVSEL# to allow a64-bit transaction to proceed. When ACK64# is not asserted with DEVSEL#, the master interfacemust revert to a 32-bit transaction. See Section 4.6.3.2 for details on 64-bit operation with 32-bittargets.A 64-bit transaction is required to have a 64-bit aligned address (AD2 = 0). A master that is startinga request on an odd boundary (AD2 = 1) must use a 32-bit transaction and not assert REQ64#.Thisis true for an initial request or as the result of a disconnect from a 32-bit target (see the nextsection). The bridge as a master on the target interface for reads will use 32-bit transactions whenthe initiator starts a 32-bit read transaction on an odd boundaryWhen ACK64# is asserted by the target of the transaction, a 64-bit transfer may proceed. As stated,a 64-bit transfer behaves exactly the same as a 32-bit transfer except that up to eight bytes of dataare transferred during each PCI data phase. For the 64-bit transfer, the AD[63:32] and C/BE[7:4]#are reserved during the address phase. (assuming a SAC transfer). During the data phases, themaster interface transfers up to eight bytes of data on each of the 8-byte lanes defined byAD[63:00]. As in a 32-bit transfer the master is capable of asserting any (or none) of the byteenables during each of the data phases within a burst transfer. Refer to Figure 4-9 for a diagram ofa 64-bit transfer to a 64-bit target. PAR64 for a 64-bit transfer has the same function and timing asPAR for a 32-bit transfer. PAR64 must be asserted one clock after each address and data phase.64-bit targets will qualify address parity checking using PAR64 with the assertion of REQ64#.Although AD[63:32] and C/BE[7:4]# are reserved for SAC 64-bit transfers, PAR64 must still bepreserved and therefore stable values must be driven.4-32 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitFigure 4-9.PCI 64-Bit Transfer to a 64-Bit TargetCLK1 2 3 4 5 6 7 8 9FRAME#REQ64#AD[31:00]ADDRESS DATA-1DATA-3 DATA-5AD[63:32]DATA-2DATA-4DATA-6C/BE[3:0]#BUS CMDBE#sC/BE[7:4]#BE#sIRDY#TRDY#WAITDATA TRANSFERWAITDATA TRANSFERWAITDATA TRANSFERDEVSEL#ACK64#ADDRESSPHASEDATAPHASEDATAPHASEDATAPHASEAs a target, the slave state machines of both bridge PCI interfaces are capable of responding as a64-bit target. When a PCI memory transaction is claimed by a bridge interface and the initiatingmaster has requested a 64-bit transfer by asserting REQ64# with FRAME#, the bridge slaveinterface will assert and deassert ACK64# with the same timing and protocol as DEVSEL#. Further64-bit slave operation is exactly like 32-bit operation with data being written or returned on bothAD[31:00] and AD[63:32] using C/BE[3:0]# and C/BE[7:4]# respectively. PAR64 must bedriven with the same timing as PAR for read operations.Developer’s Manual 4-33
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Intel 80312 I/O Companion Chip - ECEE

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