Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.8 Accelerator Descriptor Control Register - ADCRThe Accelerator Descriptor Control Register contains control values for data transfer on aper-chain descriptor basis. This read-only register is loaded when a chain descriptor is read frommemory. These values may vary from chain descriptor to chain descriptor. The AAU determineswhether a mini-descriptor is appended to the end of the current chain descriptor by examiningbits 26:25. Table 10-11 shows the definition of the Accelerator Descriptor Control Register.Table 10-11. Accelerator Descriptor Control Register - ADCR (Sheet 1 of 3)IOPAttributes31rorvrvsbci b8cc b7cc b6cc b5cc b4cc b3cc b2cc b1cc28 24 20 16 12 8 4 0rv rv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro roPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address1828HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31 0 2Destination Write Enable - Determines whether data present in the store queue is written out to Intel ®80200 processor local memory. When set, data in the queue is written to the address specified in theDestination Address Register (DAR) after performing the specified operation on data referenced by thefour SARx registers. When clear, data is held in the queue.NOTE: When the ABCR register contains a value greater than the buffer size and this bit is cleared, theAAU only reads the first buffer of bytes and perform the specified function. It does not read theremaining bytes specified in the ABCR. Further, the AAU proceeds to process the next chaindescriptor when it is specified.30:27 0H Reserved26:25 0024:22 0Supplemental Block Control Interpreter - This bit field specifies the number of data blocks on which theXOR-transfer operation is executed.00 0 Blocks - This specifies that no additional data blocks exist. The AAU does not read the mini-descriptor to initializeregisters SAR5 - SAR8.01 4 Blocks - This specifies that there are up to 4 additional data blocks. The AAU therefore reads the mini-descriptorto initialize registers SAR5 - SAR8.10 Reserved11 ReservedBlock 8 Command Control - This bit field specifies the type of operation to be carried out on the datapointedatbySAR8register.000 Null command - This implies that Block 8 Data can be disregarded for the current chain descriptor. The ApplicationAccelerator does not transfer data from this block while processing the current chain descriptor.001 XOR command - This implies that Block 8 Data is transferred to the Application Accelerator to execute the XORfunction.010 Reserved011 Reserved100 Reserved101 Reserved110 Reserved111 ReservedDeveloper’s Manual 10-31