Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitTable 12-9. I 2 C Control Register - ICR (Sheet 2 of 3)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1680HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07 0 20= EnablestheI 2 C unit to respond to general call messages.1 = Disables I 2 C unit response to general call messages as a slave.GeneralCallDisable:This bit must be set when sending a master mode general call message from the I 2 Cunit.06 0 20 = Disables the unit and does not master any transactions or respond to any slave transactions.1= EnablestheI 2 C unit (defaults to slave-receive mode).I 2 C Unit Enable:Software must guarantee the I 2 C bus is idle before setting this bit.05 0 2SCL Enable:0 = Disables the I 2 CunitfromdrivingtheSCL line.1= EnablestheI 2 C clock output for master mode operation.The ICCR (see Section 12.8.5, “I 2 C Clock Count Register- ICCR” on page 12-34) must be programmedwithavalidvaluebeforesettingthisbit.04 0 2Master Abort: usedbytheI 2 C unit when in master mode to generate a STOP without transmittinganother data byte.0= TheI 2 C unit transmits STOP using the STOP ICR bit only.1= TheI 2 C unit sends STOP without data transmission.When in Master transmit mode, after transmitting a data byte, the ICR’s Transfer Byte bit is clear andIDBR Transmit Empty bit is set. When no more data bytes need to be sent, setting master abort bitsends the STOP. The Transfer Byte bit (03) must remain clear.In master-receive mode, when a Nack is sent without a STOP (STOP ICR bit was not set) and the Intel ®80312 I/O companion chip does not send a repeated START, setting this bit sends the STOP. Onceagain, the Transfer Byte bit (03) must remain clear.03 0 2Transfer Byte: usedtosend/receiveabyteontheI 2 Cbus.0= ClearedbyI 2 C unit when the byte is sent/received.1 = Send/receive a byte.The Intel ® 80200 processor can monitor this bit to determine when the byte transfer has completed. Inmaster or slave mode, after each byte transfer including Ack/Nack bit, the I 2 C unit holds the SCL linelow (inserting wait states) until the Transfer Byte bit is set.02 0 2Ack/Nack Control: definesthetypeofAckpulsesentbytheI 2 C unit when in master receive mode.0= TheI 2 C unit sends an Ack pulse after receiving a data byte.1= TheI 2 C unit sends a negative Ack (Nack) after receiving a data byte.The I 2 C unit automatically sends an Ack pulse when responding to its slave address or when respondingin slave-receive mode, independent of the Ack/Nack control bit setting.12-28 Developer’s Manual