Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging UnitFigure 6-2 provides an overview of the Circular Queue operation.The circular queues are accessed by external PCI agents through two port locations in the PCIaddress space: Inbound Queue Port and Outbound Queue Port. The Inbound Queue Port is used byexternal PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. TheOutbound Queue Port is used by external PCI agents to read the Outbound Post Queue and writethe Outbound Free Queue. Note that a PCI transaction to the inbound or outbound queue ports withnull byte enables (P_C/BE[3:0]# = 1111 2 ) does not cause the MU hardware to increment the queuepointers. This is treated as if the PCI transaction did not occur. The Inbound and Outbound QueuePorts never respond with P_ACK64# on the primary PCI interface.Figure 6-2.Overview of Circular Queue OperationInterrupt when data inprefetch buffer is validheadOutboundPost QueuetailOutbound postedmessagesOutboundfree messagesheadHost ProcessorInboundposted messagesOutboundFree QueuetailheadInboundPost QueuetailIntel ® 80200ProcessorInterrupt whenqueue is writtenheadInboundFree QueuetailInbound freemessagesA8293-01The data storage for the circular queues must be provided by the Intel ® 80200 processor localmemory. The base address of the circular queues is contained in the Queue Base Address Register(Section 6.8.10, “Queue Base Address Register - QBAR” on page 6-27). Each entry in the queue isa 32-bit data value. Each read from or write to the queue may access only one queue entry.Multi-word accesses to the circular queues are not allowed. Sub-word accesses are promoted to32-bit word accesses.6-8 Developer’s Manual