Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.5.3 Local Memory to PCI Transfers: Memory Write andInvalidate CommandThe second mechanism for performing local memory to PCI transfers may improve systemperformance based on the PCI target capabilities. The Memory Write and Invalidate (MWI)command improves system performance when the target is cacheable memory.The DMA channel attempts to use the Memory Write and Invalidate command on the PCI buswhenever programmed by the application software. The DMA channel requests the PCI bus once acomplete cache line is available in the DMA queue. However, there are a number of circumstanceswhich may prevent the DMA channel from actually initiating the MWI command. It is theresponsibility of the application software to meet the requirements for the MWI command.When any of the following three conditions is not met, the channel converts the MWI command toa Memory Write command for the complete DMA transfer:1. The ATU Cacheline Size Register (ATUCLSR), located in the ATU configuration space, musthave a valid value other than zero. This register is programmed by host software.2. The ATUCLSR must have a legal value which is less than or equal to the number of queueentries in the DMA channel queue. (The channel must guarantee an entire cache line can betransferred during an MWI bus transaction).3. The Memory Write and Invalidate Enable bit in the Primary ATU Command Register (forchannels 0 and 1) or the Secondary ATU Command Register (for channel 2) must be set.When the above conditions are met, the DMA channel provides full MWI support. For example, totransfer an 80 byte block to a PCI address of 8001CH while the ATUCLSR is 8 DWORDs, theDMA channel performs three PCI transactions:1. Transfer of 4 bytes at address 8001CH using the Memory Write command.2. Transfer of 64 bytes at address 80020H using the MWI command.3. Transfer of 12 bytes at address 80060H using the Memory Write command.9.5.4 Exclusive AccessThe DMA Controller does not support exclusive access through the PCI LOCK# signal.9.6 Data QueuesDMA Ch-0 and Ch-1 each contain a 256-byte, bidirectional data queue. DMA Ch-2 on thesecondary side contains a 64-byte, bidirectional data queue. These queues temporarily hold data toincrease performance of data transfers in both directions.9-16 Developer’s Manual