Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitData flow for the inbound write transaction on the internal bus is summarized as:• The ATU internal bus master requests the internal bus when the IWQAD/IWQ contains thePCI address and data for the current transaction which has crossed at least a 2 QWORDboundary or a PCI address from an earlier posted PCI transaction has moved to the head of theIWQAD.• When the internal bus is granted, the internal bus master interface initiates the writetransaction by driving the translated address onto the internal bus. For details on inboundaddress translation, see Section 5.2, “ATU Address Translation” on page 5-4. Ifnodeviceclaims the transaction, a master abort condition is signaled on the internal bus. The currenttransaction is flushed from the queue and SERR# on the PCI interface is asserted based uponthe setting of the ATUCR, see Section 5.7.37, “ATU Configuration Register - ATUCR” onpage 5-98.• Write data is transferred from the IWQ to the internal bus when data is available and theinternal bus interface retains internal bus ownership. The ATU master interface attempt a64-bit transfer. If not accepted, a 32-bit transfer is used. Transfers of less than 64-bits use thebyte enables to mask the bytes not written in the 64-bit data phase.• The internal bus interface stops transferring data from the current transaction to the internalbus when one of the following conditions becomes true:— The internal bus master interface loses bus ownership and the master latency timer hasexpired. The ATU internal master performs a master completion and attempt to reacquirethe bus to complete delivery of the data.— A Disconnect with Data is signaled on the internal bus from the internal slave. If thetransaction in the IWQ is complete, the master returns to idle. If the transaction in theIWQ is not complete, the master attempts to reacquire the internal bus.— The data from the current transaction has completed. A master completion is performedand the bus returns to idle.— A Target Abort is signaled from the internal bus slave. This is in response to an ECC errorfrom the memory controller. SERR# is asserted based upon the setting of the PATUIMRor the SATUIMR, see Section 5.7.50, “Primary ATU Interrupt Mask Register -PATUIMR” on page 5-114 and Section 5.7.51, “Secondary ATU Interrupt Mask Register -SATUIMR” on page 5-115. A disconnect is signaled on PCI when the transaction isactive. If the transaction in the IWQ is complete, the master returns to idle. If thetransaction in the IWQ is not complete, the master attempts to reacquire the internal bus.Refer to Section 5.6.6.2, for full details.— A Master Abort is signaled on the internal bus. SERR# is asserted based upon the settingofthePATUIMRortheSATUIMR,seeSection 5.7.50, “Primary ATU Interrupt MaskRegister - PATUIMR” on page 5-114 and Section 5.7.51, “Secondary ATU Interrupt MaskRegister-SATUIMR”onpage5-115. Data is flushed from the IWQ.• When the ATU attempts to transfer data in the IWQ to the IB and is stopped during a burst forany reason other than a Master Abort, the ATU attempts to reacquire the IB only after one ofthe following conditions is met:— The transactions has disconnected on the PCI bus.— At least 4 Dwords are in the IWQ.— The next IB address to attempt is not Qword aligned.5-10 Developer’s Manual