Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.2.3 Internal Bus ResetThe Reset Internal Bus bit in the Extended Bridge Control Register resets the Intel ® 80200processor and all units on the internal bus. Before resetting, the DMA channels and the ATUs shallgracefully halt all PCI bus transactions. It is the responsibility of the software to ensure that the I 2 Cbus is idle before the reset occurs. The Intel ® 80200 processor may or may not be held in resetwhen the Reset Local Bus bit is cleared by software. This depends on the default value of the Intel ®80200 processor Reset bit in the EBCR. The Local Bus Reset does not reset the PCI to PCI BridgeUnit or its configuration registers.When the reset internal bus bit in the Extended Bridge Control Register is set, there are sidebandsignals notifying the CIU, PATU, SATU, and the DMAs that a reset is coming. The followingdescribes the operation of each unit:Table 15-5. Internal Bus Reset Summary (Sheet 1 of 2)Unit Preparation for Reset Reset StatusPATU/SATU/MUThe ATUs and MU detect via a sideband signal that a internalbus reset is coming. Upon detecting this signal, the ATUsand MU:PCI Interface Outbound Transaction:• When the ATUs has already asserted its PCI requestsignal, and not yet started a transaction, the ATUsdeasserts its request and not start its transaction.• When the ATUs has not yet requested the PCI bus, theATUs never asserts its request for the PCI bus.• When the ATUs is in the middle of a transaction, theATUs perform the existing transaction. This means thatan inbound write, the ATUs transfer as much data asavailable in the queue. When an outbound read, theATUs read the data until the transaction stops naturally(meaning that the target has ended the transaction or theATU has read all of the data it has been requested toread). However, when the SATU is retried ordisconnected, the SATU does not try to re-initiate thetransaction. Once terminated by the ATU or the target,theATUsnolongerrequestthePCIbus.PCI Interface Inbound Transaction:• Once the ATUs and MU have detected that an internalbus reset is coming, they no longer claim any newtransactions on the PCI bus. This results in a masterabort to the initiating master.• The other requirement for the inbound ATU is tocomplete the configuration cycle which set the IB resetbit in the bridge configuration space.Internal Bus Interface: Inbound Transaction:• When the ATUs and MU goes ahead and asserted its IBrequest signal, and try to continue the transaction asnormal. There are no special actions taken on theinternal bus for inbound transactions.Internal Bus Interface: Outbound Transaction:• For all ATUs and MU outbound transactions, there areno special requirements since the CIU/Intel ® 80200processor is reset.Upon meeting both the outbound and inbound transactionrequirements, the ATUs and MU asserts the sideband signalto the reset unit notifying ready-for-reset.Clear all ATUs and MU interruptsand IRQs. All ATUs and MU MMRsreset to the default value.Developer’s Manual 15-11