Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring UnitTable 11-7. Event Monitoring Interrupt Status Register (EMISR) (Sheet 2 of 2)IOPAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrcrcrcrcrcrcrcrcrcrcPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na31 28 24 20 16 12 8 4 0Intel ® 80200 Processor Local Bus AddressAttribute Legend: RW = Read/Write0000 1108HRV = Reserved RC = Read ClearPR = Preserved RO = Read OnlyRS = Read/Set NA = Not AccessibleBit Default Description7 0 2Bit value indicates the status of the Programmable Event Counter 7 (PEC7) during event monitoring.When clear (0), no PEC7 overflow interrupt is pending. When set (1), a PEC7 overflow interrupt ispending.6 0 2Bit value indicates the status of the Programmable Event Counter 6 (PEC6) during event monitoring.When clear (0), no PEC6 overflow interrupt is pending. When set (1), a PEC6 overflow interrupt ispending.5 0 2Bit value indicates the status of the Programmable Event Counter5 (PEC5) during event monitoring.When clear (0), no PEC5 overflow interrupt is pending. When set (1), a PEC5 overflow interrupt ispending.4 0 2Bit value indicates the status of the Programmable Event Counter4 (PEC4) during event monitoring.When clear (0), no PEC4 overflow interrupt is pending. When set (1), a PEC4 overflow interrupt ispending.Bit value indicates Programmable Event Counter3 (PEC3) status during event monitoring. When clear3 0 2 (0), no PEC3 overflow interrupt is pending. When set (1), a PEC3 overflow interrupt is pending.2 0 2 When clear (0), no PEC2 overflow interrupt is pending. When set (1), a PEC2 overflow interrupt isBit value indicates the status of the Programmable Event Counter2 (PEC2) during event monitoring.pending.1 0 2Bit value indicates the status of the Programmable Event Counter1 (PEC1) during event monitoring.When clear (0), no PEC1 overflow interrupt is pending. When set (1), a PEC1 overflow interrupt ispending.Bit value indicates the status of the Global Time Stamp Counter (GTS) during event monitoring. When0 0 2 clear (0), no GTS overflow interrupt is pending. When set (1), a GTS overflow interrupt is pending.11-26 Developer’s Manual