Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.4.5 ECC TestingThe MCU implements the ECTST register providing the programmer the ability to test errorhandling software. For write transactions, the ECTST register value is XORed with the generatedECC. This inverts the bits where the mask is set prior to writing the ECC to memory. When theMCU reads the address later, the ECC mismatches and the error condition occurs (see Section 3.4,“Interrupts/Error Conditions” on page 3-41).3.2.5 Overlapping Memory RegionsThe MCU supports four independent memory regions:• MMR Memory Space• SDRAM Memory Space• Two Flash Memory SpacesThe MMR memory space is fixed at 1500H to 15FFH. Software programs the SDRAM memoryregion by providing a base address in SDBR and each of the two bank boundaries in SBR0 andSBR1. The first Flash address range is programmed with a base register in FEBR0 and the banksize in FBSR0. FEBR1 and FBSR1 defines the second address range.While it is not recommended, the four ranges could overlap. In the case of a memory regionoverlap, refer to Table 3-14 for the priority rules.Table 3-14.Overlapping Address PrioritiesPriorityAddress RegionHighestMemory Mapped Register Address SpaceFlash Bank 0 Address SpaceFlash Bank 1 Address SpaceLowestSDRAM Address SpaceDeveloper’s Manual 3-33