Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI Address Translation UnitFigure 5-9.64-Bit Write Request with 32-Bit TransferCLK1 2 3 4 5 6 7 8 9FRAME#REQ64#AD[31:00]ADDRESSDATA-1DATA-2DATA-3AD[63:32]DATA-2C/BE[3:0]#BUS CMDBE#’s-1 BE#’s-2 BE#’s-3C/BE[7:4]#BE#’s-2IRDY#TRDY#DATA TRANSFERDATA TRANSFERWAITWAITWAITDATA TRANSFERDEVSEL#ACK64#ADDRESSPHASEDATAPHASEDATAPHASEDATAPHASE5-28 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.6 66 MHz OperationBoth the PATU and the SATU of the Intel ® 80312 I/O companion chip are capable of PCI 66 MHzoperation to support data transfer rates of up to 264 MBytes/sec with a 32-bit bus or 528Mbytes/sec with a 64-bit bus. Differences between 33 MHz PCI and 66 MHz PCI are minimal.Both share the same protocol, and signal definitions. The 66 MHz PCI extension adds oneadditional signal to each PCI interface. The signal and its function is• M66EN - when asserted for a PCI interface, indicates that interface runs at 66 MHzAdditionally, bit 5 of the Primary ATU Status Register - PATUSR is set to a 1 2 indicating that thePATU is capable of 66 MHz operation.At PCI bus reset, each individual PCI bus (primary and secondary) independently samples theirrespective M66EN signals. If this signal is high, the bus is 66 MHz capable, and in the case of theprimary bus, the clock unit is configured to accept a 66 MHz Primary PCI Bus clock.The 66 MHz capable Intel ® 80312 I/O companion chip supports the following primary andsecondary bus frequency combinations:• 66 MHz primary bus, 66 MHz secondary bus• 66 MHz primary bus, 33 MHz secondary bus• 33 MHz primary bus, 33 MHz secondary busThe Intel ® 80312 I/O companion chip does not support 33 MHz primary/66 MHz secondary busoperation, where the secondary bus is operating at twice the frequency of the primary bus. IfP_M66EN is low (primary bus at 33 MHz), then the Intel ® 80312 I/O companion chip pulls downS_M66EN to indicate that the secondary PCI bus is operating at 33 MHz.The Intel ® 80312 I/O companion chip generates clock signals S_CLKOUT[6:0] for the secondarybus devices and its own secondary interface (S_CLKIN). TheIntel ® 80312 I/O companion chipdivides the primary bus clock P_CLK by two to generate the secondary bus clock outputswhenever the primary bus is operating at 66 MHz and the secondary bus is operating at 33 MHz.The Intel ® 80312 I/O companion chip detects this condition when P_M66EN is high andS_M66EN is low.For more details on the Intel ® 80312 I/O companion chip’s 66 MHz PCI clock scheme and theoperation of the secondary PCI bus clocks, please see Chapter 15, “Clocking, Reset, andInitialization”.Developer’s Manual 5-29
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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DMA Controller Unit 9This chapter d
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Intel 80312 I/O Companion Chip - ECEE

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