Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.5 Reset ConditionsThe Global Time Stamp Counter is cleared upon deassertion of the Internal Bus Reset signal. TheGlobal Timer Mode Register (GTMR) is cleared on reset. The Event Select Register (ESR) defaultsto Mode 0 upon reset: performance monitoring is disabled and all counters are disabled in thismode. The Programmable Event Counters (PECRx) values are undefined upon reset.11.6 Register DefinitionsThe performance monitoring facility on Intel ® 80312 I/O companion chip consists of eighteen (18)memory-mapped registers for controlling operation and monitoring various events. Each register is32-bits wide. Each of these registers is accessed as a memory-mapped 32-bit register with a uniquememory address. Access is accomplished through regular memory-format instructions from theIntel ® 80200 processor.Three registers control the mode of operation. They are; Global Timer Mode Register (GTMR),Event Monitoring Interrupt Status Register (EMISR), and the Event Select Register (ESR). TheGTMR controls operation of the Global Time Stamp Counter. The EMISR is used to indicate anoverflow condition in any counter during performance monitoring. An overflow condition in theGlobal Time Stamp Counter is also indicated in the EMISR when the mode is enabled. The valueprogrammed into the Event Select Register (ESR) determines the monitored interface.Fourteen(14) registers(PECR1 - PECR14) contain the current count value from the programmableevent counters (PEC1 - PEC14). The Global Time Stamp Register (GTSR) contains the currentcount value of the Time Stamp Counter. The event registers (PECR1 - PECR14) and the GTSR areread-only registers.Table 11-4 identifies the registers used for performance monitoring. Each register is described inthe subsections following Table 11-4.Table 11-4.Event Monitor Register TableSection, Register Name - Acronym (Page)Section 11.6.1, “Global Timer Mode Register (GTMR)” on page 11-23Section 11.6.2, “Event Select Register (ESR)” on page 11-24Section 11.6.3, “Event Monitoring Interrupt Status Register (EMISR)” on page 11-25Section 11.6.4, “Global Time Stamp Register (GTSR)” on page 11-27Section 11.6.5, “Programmable Event Counter Register (PECRx)” on page 11-2811-22 Developer’s Manual