Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMemory Controller3.2.2.2 Flash Read CycleReading a Flash device involves driving the address, output enable, and chip enable. Depending onthe speed of the Flash device, the data returns several cycles later.The definition of address-to-data wait states are the number of cycles between the assertion ofRCE[1:0]# or ROE# (whichever is last), and the arrival of data from the Flash or UART device onRAD[16:9]. The definition of recovery wait states are the number of cycles between the dataarrival on RAD[16:9] and the address for the next Flash transaction.Address-to-data and recovery wait states programmed in FWSR0 and FWSR1 are identical forreads and writes. Since the read wait state requirement is typically greater, the write wait staterequirement is guaranteed to be met. Refer to Table 3-4 for the programmable address-to data andrecovery wait states.Figure 3-3 illustrates a read cycle from a 90 ns Flash device.Figure 3-3.90 ns Flash Read CycleDCLKRCE#ROE#RWE#RAD[2:0]T A T A T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T D T R T R T R T R0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ADDR[2:0]20RAD[8:3]ADDR[22:17]ADDR[8:3]AD[16:9]RALEADDR[16:9]D 0Address 14-bit External LatchDecodeRetry the Internal BusWhen an internal bus master requests data from the Flash memory region, the MCU decodes theinternal bus byte enables for the initial RAD[2:0]. The read request could result in multiple 8-bitreads (burst) on the Flash interface depending on the byte enables. The Flash state machineincrements RAD[2:0] for each read. The MCU is responsible for packing the multiple bytes andplacing them on the appropriate byte lanes before driving the data on the internal bus. Due to thetypically long time for Flash reads, the master reading data always ges disconnected after the firstdata phase.3-8 Developer’s Manual
Intel ® 80312 I/O Companion ChipMemory ControllerFigure 3-4 illustrates a bursted read cycle from a 60 ns Flash device.Figure 3-4.60 ns Flash Burst Read CycleT AT AT DDCLKRCE#ROE#RWE#RAD[2:0]RAD[8:3]RAD[16:9]13 14 15 160 1 2 3 4 5 6 7 8 9 10 11 12T 1 T 2 T 3 T 4 T D T 1 T 2 T 3 T 4ADDR[16:9]D 0 D 1ADDR[2:0]ADDR[2:0] + 1ADDR[22:17]ADDR[8:3]RALEAddressDecode14-bit ExternalLatchD 0 drivenby Flash andlatchedintheMCUPack D 0 and D 1and drive on InternaRefer to Table 3-4 for the programmable address-to data wait states.Table 3-4.Flash Wait State Profile ProgrammingFlash Speed Address-to-Data Wait States Recovery Wait States
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Messaging Unit 6This chapter descri
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Application Accelerator Unit 10This
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General Purpose Input Output (GPIO)
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Intel 80312 I/O Companion Chip - ECEE

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