Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipGeneral Purpose Input Output (GPIO)Table 13-1. GPIO Output Enable Register - GPOE (Sheet 2 of 2)IOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesnanananananananaIntel ® 80200 Processor Local Bus Address0000 171CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description050403020100GPIO[5]duringP_RST#assertionGPIO[4]duringP_RST#assertionGPIO[3]duringP_RST#assertionGPIO[2]duringP_RST#assertionGPIO[1]duringP_RST#assertionGPIO[0]duringP_RST#assertionGPIO5 Output Enable -- When clear, bit 5 of GPIO Output Data Register is enabled onto GPIO[5] pin.GPIO4 Output Enable -- When clear, bit 4 of GPIO Output Data Register is enabled onto GPIO[4] pin.GPIO3 Output Enable -- When clear, bit 3 of GPIO Output Data Register is enabled onto GPIO[3] pin.GPIO2 Output Enable -- When clear, bit 2 of GPIO Output Data Register is enabled onto GPIO[2] pin.GPIO1 Output Enable -- When clear, bit 1 of GPIO Output Data Register is enabled onto GPIO[1] pin.GPIO0 Output Enable -- When clear, bit 0 of GPIO Output Data Register is enabled onto GPIO[0] pin.Developer’s Manual 13-3