Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip Arbitration7.2.1.4 Arbitration Signalling ProtocolThe PCI Arbiter interfaces to all requesting agents on the bus through the REQ#/GNT#handshaking protocol. A bus master asserts its REQ# to request ownership of the PCI bus. Whenthe arbiter determines an agent may use the bus, it asserts the agent’s GNT# input. Agents mustonly assert its REQ# to signal a true need for the bus and not to reserve the bus. Figure 7-3illustrates secondary arbitration between masters of equal priority.Figure 7-3.Arbitration Between Two MastersS_CLKIN1 2 3 4 5 6 7 8 9 10 11 12S_REQ(0)#S_REQ(1)#S_GNT(0)#S_GNT(1)#S_FRAME#S_IRDY#S_TRDY#S_AD(63:0) Addr 0 D 0 D 1 D 2 Addr 1 D 0 Addr 0 D 0A6767-01An agent can be granted the bus while a previous bus owner still has control of the PCI bus (hiddenarbitration). The arbiter is responsible for deciding which PCI device is granted the bus next whileeach master is responsible for determining when the PCI bus actually becomes free and is allowedto initiate its transaction by asserting FRAME#.The PCI Local Bus Specification, Revision 2.2 indicates that a master may deassert its REQ# pinbefore the arbiter grants the PCI bus to that master. If a master deasserts its REQ# pin, the PCIArbiter re-arbitrates and give bus ownership to the next master based on the priority algorithmdefined in Section 7.2.1.1, “Priority Mechanism” on page 7-3.The PCI Arbiter may deassert an agent’s GNT# on any clock. An agent must ensure its GNT# isasserted on the clock edge where it initiates a transaction by asserting FRAME#. IfGNT# isdeasserted, the transaction may not proceed.7-6 Developer’s Manual