Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.5.3 Intel ® 80200 Processor Request Bus Read from the InternalBusThe Intel ® 80200 processor request bus issues a read command for 8 bytes of data from theinternal bus.1. On the rising-edge of clock 1, the Intel ® 80200 processor asserts active low ADS# to indicatea valid request bus command. The Intel ® 80200 processor (for read) asserts active low W/R#.The LOCK# signal is deasserted indicating that the read is not initiating a locked atomic readmodify write operation.2. Concurrent with the rising clock edge above, the Intel ® 80200 processor asserts the mostsignificant 16 bits of address on ADD[15:0]. This address is translated by the CIU to internalbus address bits [31:16] (I_AD[31:16]).3. On the rising edge of clock 2, the Intel ® 80200 processor asserts the request transfer length onADS#, W/R# and LOCK#. The least significant 16 bits of address are driven on ADD[15:0].This address is translated by the CIU to internal bus address bits [15:0].4. The CIU issues a request for ownership of the internal PCI bus to the arbiter.5. The Arbiter grants ownership of the internal bus to the CIU.6. The CIU asserts the C_HOLDMCU sideband signal to obtain ownership of the SDRAM bus.7. The MCU acknowledges that it is ready to perform the CIU transaction by asserting theM_HOLDACK sideband signal.8. The CIU asserts frame on the internal bus and supplies the appropriate PCI command -“memory read” for a transaction of less than 8 bytes, “memory read line for an 8 bytetransaction, and “memory read multiple” for requests greater than 8 bytes.9. The CIU asserts the internal bus I_IRDY# signal indicating that as initiator it is ready toreceive data.10. The internal bus target claims the internal bus transaction by asserting I_DEVSEL#.11. The internal bus target asserts the I_TRDY# signal to indicate valid data is transferred.12. The CIU asserts the Intel ® 80200 processor request bus C_DVALID signal to indicate thatdata transferred on DQ[63:0] and check bits transferred on SCB[7:0] are valid in two clockcycles. C_DVALID is asserted for one clock period for each cycle of data to be transferred inthe burst.13. The Intel ® 80200 processor registers the read data and check bits. Check bits needed forSDRAM error detection and correction are not driven by the CIU.14. Having deasserted C_DVALID and transferred the requested data to the Intel ® 80200processor, the CIU deasserts C_HOLDMCU.15. The MCU deasserts M_HOLDACK to complete the transaction.16. The CIU clears the current request register and executes the next pending request buscommand. If no requests are pending the CIU returns to the idle state where it waits for thenext Intel ® 80200 processor request.8-10 Developer’s Manual