Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.3.7 M2_DMA2_acqThis duration event counts number of clocks spent by DMA Ch-2 acquiring PCI interface. Thecounter increments every clock cycle after the channel requests the PCI bus, but has not activelydriven the PCI bus as master. The counter also increments for all clock cycles when agent RequestSignal is asserted, but bus ownership currently belongs to another master. This is an eventprimitive, used in conjunction with another event primitive (number of grants granted to DMACh-2) to calculate average acquisition latency for the channel.11.3.3.8 M2_DMA2_ownThis duration event counts the duration for which DMA Ch-2 is the master on the PCI interface.The counter increments on every clock cycle during which the channel is the bus master.11.3.3.9 M2_bridge_gntThis occurrence event monitors number of times the bridge is granted the secondary PCI bus. Thisevent increments the counter when the bridge is the PCI bus master. The counter is incremented oncefor every new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.3.10 M2_SATU_gntThis occurrence event monitors the number of times the SATU is granted the PCI bus. This eventincrements the counter when the unit is the PCI bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.3.11 M2_DMA2_gntThis occurrence event monitors the number of times DMA Ch-2 is granted the PCI bus. This eventincrements the counter when the channel is the PCI bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.3.12 M2_PPCIBus_idleThis duration event increments the counter every primary PCI idle cycle. An idle cycle occurswhen there is no activity on the bus due to data being transferred and/or the bus is not in anoverhead cycle. An overhead cycle is a cycle when a master owns the bus, however the master isunable to send data or the target is unable to receive data - hence no data is transferred.11.3.3.13 M2_PPCIBus_busyDuration event increments counter every primary PCI data cycle. Data cycles comprise two instances:• Intel ® 80312 I/O companion chip as master on bus involves in data transfers to other masters.• External masters initiate data transfers to either Intel ® 80312 I/O companion chip or other masterson the bus.11.3.3.14 M2_IBus_busyThis duration event increments the counter on every internal bus data cycle. This enablescalculation of data utilization of the bus.11-10 Developer’s Manual