Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.3 Reset Strapping OptionsThere are many initialization modes that can be selected when the processor is reset. Table 15-6shows the configuration modes that are customer visible. All of the configuration modes definedare determined on the rising edge of P_RST#.Table 15-6.Reset Strap SignalsNAMERAD[6]/RST_MODE#RAD[5]/ONCE#RAD[3]/RETRYRAD[2]/SPMEM#RAD[1]/32BITPCI_EN#DESCRIPTIONRESET MODE is sampled at Primary PCI bus reset to determine when the Intel ®80312 I/O companion chip is to be held in reset. When asserted, the Intel ® 80312I/O companion chip is held in reset until the Intel ® 80200 Processor Reset bit iscleared in the Extended Bridge Control Register.ONCE MODE: The device samples this pin during reset to place have theprocessor stop all clocks and float all output pins except the TDO pin.RETRY is sampled at Primary PCI bus reset to determine when the Primary PCIinterface is disabled. When high, the Primary PCI interface disables PCIconfiguration cycles by signaling a Retry until the Configuration Cycle Retry bit iscleared in the Extended Bridge Control Register. When low, the Primary PCIinterface allow configuration cycles to occur.SPECIAL MEMORY WINDOW: The processor samples this pin during PrimaryBus reset to determine when the PCI-to-PCI Bridge Unit’s Special Memory Windowis open or closed by default.When SPMEM# is high, the Special Memory Window (FEC0_0000h --FECF_FFFFh) is closed by default.When SPMEM# is low, the Special Memory Window (FEC0_0000h --FECF_FFFFh) is open by default.Please see section 4.5.4, Special Memory Window Support for External Hot-PlugControllers (pg. 4-21) in Chapter 4, “PCI-to-PCI Bridge Unit” for more details.32-BIT Secondary PCI Enable The 32BITPCI_EN# signal is sampled at PrimaryPCI Reset to notify the secondary PCI arbiter NOT to generate the 64-bit protocolafter the rising edge of the secondary reset for the secondary PCI bus.When 32BITPCI_EN# is high, the secondary PCI arbiter asserts SREQ64# duringS_RST#, indicating the secondary PCI bus is a 64-bit bus.When 32BITPCI_EN# is low, the secondary PCI arbiter does not assert SREQ64#during S_RST#, indicating the secondary PCI bus is NOT a 64-bit bus.Developer’s Manual 15-13