Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.8 Bridge Data FlowThe bridge allows transactions to cross both PCI buses through the Intel ® 80312 I/O companionchip. PCI transactions initiated on the Primary PCI bus and targeted at an agent on the SecondaryPCIbusarereferredtoasdownstream transactions and PCI transactions initiated on the SecondaryPCIbusandtargetedatanagentonthePrimaryPCIbusarereferredtoasupstream transactions.Upstream and downstream bridge transactions are best described by the data flows used on theinitiating and target bus during read and write operations. The following sections describe:• Delayed Read transactions• Delayed Write transactions• Posted Write transactionsSeparate upstream and downstream transactions are not shown but have identical data flows exceptthat the references to initiating interface and target interface are reversed.4.8.1 Delayed Read TransactionA delayed read transaction is initiated by a PCI master on the initiating PCI bus and is targeted at aPCI agent on the target PCI bus. The read transaction is propagated through the bridge and readdata is returned through a Delayed Read Completion Queue (DRC).All read transactions are processed as delayed read transactions. The PCI slave interface on theinitiating bus of the bridge claims the read transaction and store the read address and controlinformation in a bridge Transaction Queue. This read request is then forwarded to the target bus. Thetarget bus master interface then performs the read from a PCI target and store returning read data in aDelayed Read Completion Queue. The original PCI master on the initiating bus continuously retriesthe read transaction until slave interface on initiating bus claims the transaction and returns read datapresent in the DRC Queue. The data flow for a delayed read transaction is summarized as followings:• The Bridge claims the PCI read transaction when the PCI address is within the addresswindow defined by a Base/Limit register pair and a Transaction Queue is available to retainthe address/control information to forward to the target bus.• When there is currently an available Transaction Queue, then latch the PCI address intoTransaction Queue and then signal a Retry to the initiator.• When an address parity error is detected, allow transaction to master-abort and assert SERR#.This assumes parity checking is enabled and SERR# assertion is enabled (Note: SERR# is notasserted on Secondary bus interface, only on the Primary bus interface, see Section 4.11.1).• When transaction inside address window and Transaction Queue not available or inside an addresswindow, a cycle match occurs, but read data not ready (!DRC_Ready), then retry transaction.• When transaction is inside an address window, a cycle match occurs, read data is ready in theDRC (DRC_Ready), then returns read data to the master device. Data is returned 64-bits widewhen the master used REQ64# during request or 32-bits when REQ64# was not asserted.• Once read data has started to be driven onto the initiating PCI bus from a DRC Queue, it willcontinue to be driven until one of the following is true:— The initiator completes the PCI transaction, master-completion.— The DRC Queue becomes empty.— A target-abort condition is driven out from the DRC Queue.• When a data parity error is detected by the master and PERR# is asserted, set the appropriateerror response bits (when enabled, see Section 4.11.2).Developer’s Manual 4-55