Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.13 Expansion ROM Base Address Register - ERBARThe Expansion ROM Base Address Register defines the block of memory addresses used forcontaining the Expansion ROM. It permits the inclusion of multiple code images, allowing thedevice to be initialized. The code image supplied consists of either executable code or aninterpreted code. Each code image must start on a 512 byte boundary and each must contain thePCI Expansion ROM header. Image placement in ROM space depends on the length of codeimages which precede it within ROM. ERBAR defines the base address and describes the requiredmemory block size; see Section 5.7.15. Expansion ROM address space (limit size) can be amaximum of 16 MBytes. Bits 31 through 12 of the ERBAR is either read/write bits or read onlywith a value of 0 depending on the value located within the ERLR. This configuration allows theERBARtobeprogrammedperPCI Local Bus Specification, Revision 2.2.The Expansion ROM Base Address Register’s programmed value must comply with the PCIprogramming requirements for address alignment. Refer to the PCI Local Bus Specification,Revision 2.2 for additional information on programming Expansion ROM base address registers.Table 5-40.Expansion ROM Base Address Register -ERBARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rwPCIAttributesrw rw rw rw rw rw rw rwrw rw rw rw rw rw rw rwrw rw rw rwrvrvrvrvrvrvrvrvrvrvrvrwIntel ® 80200 Processor Local Bus Address1230HPCI Configuration Address Offset30H - 33HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 00000HExpansion ROM Base Address - These bits define the actual location where the Expansion ROMaddress window resides when addressed from the primary PCI bus on any 4 Kbyte boundary.11:01 000H ReservedAddress Decode Enable - This bit field shows the ROM address decoder is enabled or disabled. When00 0 2 cleared, indicates the address decoder is disabled.5-74 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.14 ATU Capabilities Pointer Register - ATU_Cap_PtrThe Capabilities Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2. This register provides an offset in this function’s PCI Configuration Space for thelocation of the first item in the Capabilities linked list. In the case of the Intel ® 80312 I/Ocompanion chip, this is the PCI Bus Power Management extended capability as defined by the PCIBus Power Management Interface Specification, Revision1.1.Table 5-41.ATU Capabilities Pointer Register - ATU_Cap_PtrIOPAttributes7 4 0ro ro ro ro ro ro ro roPCIAttributesrorororororororoIntel ® 80200 Processor Local Bus Address0000 1234HPCI Configuration Address Offset34HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not Accessible36BitDefaultDescription07:00 80HCapability List Pointer - This provides an offset in this function’s configuration space that points to theIntel ® 80312 I/O companion chip’s PCl Bus Power Management extended capability.Developer’s Manual 5-75
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Intel ® 80200 Processor based on I
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DMA Controller Unit 9This chapter d
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Application Accelerator Unit 10This
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Intel 80312 I/O Companion Chip - ECEE

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