Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.6.5 I/O Write CommandAll I/O Write transactions will be processed as Delayed transactions. The Intel ® 80312 I/Ocompanion chip is restricted to 16-bit addressing for I/O transactions although it still must decodethe full 32-bits of address and verify that AD[31:16] = 0000H. The bridge will claim anytransaction inside the 16-bit address range defined by the I/O Base and I/O Limit registers on thePrimary bus and outside the address range on the Secondary address bus.4.6.6.6 Write BoundaryThe bridge of the Intel ® 80312 I/O companion chip imposes a naturally-aligned 4096-byte writeboundary for posted write transactions only. When the bridge unit detects a write boundary, theinitiating interface will signal a Disconnect to the initiator and complete delivery of the write datawithin the PMW Queue to the target interface. The write boundary can be considered an addresscounter which is incremented by one for every byte of a burst transaction. The write boundary isimposedwhenthelower12bitsofthecounterreachzero.4.6.6.7 Qword Unaligned Memory Write TransactionsTo minimize the number of null write transactions on the PCI bus, the bridge has the followingbehavior for Qword (8-byte) unaligned write transactions:• When the memory write transaction is completely posted within the bridge posted memorywrite queue (upstream or downstream), and the transaction is QWORD aligned at both thehead and tail of the transaction, then the bridge will attempt this as a 64-bit transaction(assuming the bus is defined as 64-bit).• When the memory write transaction is in a streaming mode (active on initiating bus while thetarget interface is acquired), the bridge will attempt the transaction on the target bus based onthe initiating bus transaction width:— 64-bit memory write transaction on initiating bus is attempted as a 64-bit transaction onthe target bus— 32-bit memory write transaction on initiating bus is attempted as a 32-bit transaction onthe target bus4.6.6.8 Fast Back-to-Back TransactionsThe Intel ® 80312 I/O companion chip bridge unit does not generate fast back to back transactions.TheFastBacktoBackEnablebitsinthePrimaryCommandRegister(PCR)andintheBridgeControl Register (BCR) are ignored.The bridge unit is capable of accepting fast back to back transactions from the same PCI master.4-46 Developer’s Manual