Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip4.6.4 66 MHz Operation...................................................................................................4-364.6.5 PCI Read Transactions...........................................................................................4-374.6.5.1 Read Streaming ........................................................................................4-414.6.5.2 Read Boundary .........................................................................................4-414.6.6 PCI Write Transactions...........................................................................................4-424.6.6.1 Delayed Write Transactions......................................................................4-424.6.6.2 Posted Write Transactions........................................................................4-434.6.6.3 Memory Write Command ..........................................................................4-444.6.6.4 Memory Write and Invalidate Command...................................................4-454.6.6.5 I/O Write Command ..................................................................................4-464.6.6.6 Write Boundary .........................................................................................4-464.6.6.7 Qword Unaligned Memory Write Transactions .........................................4-464.6.6.8 Fast Back-to-Back Transactions ...............................................................4-464.7 Queue Architecture..................................................................................................................4-474.7.1 Queue Operation ....................................................................................................4-484.7.1.1 Upstream/Downstream Posted Memory Write Queue Structures ............4-494.7.1.2 Upstream/Downstream Delayed Read Completion Queues.....................4-504.7.1.3 Upstream/Downstream Delayed Write Completion Queue.......................4-514.7.1.4 Upstream/Downstream Transaction Queues ............................................4-524.7.2 Transaction Ordering..............................................................................................4-524.8 Bridge Data Flow .....................................................................................................................4-554.8.1 Delayed Read Transaction .....................................................................................4-554.8.2 Delayed Write Transaction .....................................................................................4-574.8.3 Posted Write Transaction .......................................................................................4-594.9 Exclusive Access.....................................................................................................................4-614.9.1 Secondary Interface Error Handling .......................................................................4-624.10 PCI Transaction Termination...................................................................................................4-634.10.1 Termination as a Master (Initiator)..........................................................................4-634.10.1.1 Completion................................................................................................4-634.10.1.2 Time-out....................................................................................................4-634.10.1.3 Time-out During Memory Write and Invalidate .........................................4-634.10.1.4 Master-Abort .............................................................................................4-644.10.2 Termination as a Slave (Target) .............................................................................4-644.10.2.1 Retry .........................................................................................................4-644.10.2.2 Disconnect ................................................................................................4-654.10.2.3 Target-Abort..............................................................................................4-654.11 Error Conditions.......................................................................................................................4-664.11.1 Address Parity Errors..............................................................................................4-664.11.1.1 Address Parity Errors on Primary Interface ..............................................4-664.11.1.2 Address Parity Errors on Secondary Interface..........................................4-674.11.2 Data Parity Errors ...................................................................................................4-684.11.2.1 Read Data Parity.......................................................................................4-684.11.2.2 Delayed Write Data Parity.........................................................................4-694.11.2.3 Posted Write Data Parity...........................................................................4-714.11.3 SERR# Assertion....................................................................................................4-724.11.4 Discard Timers........................................................................................................4-734.11.5 PCI-to-PCI Bridge Error Summary..........................................................................4-744.12 Initialization and Reset Requirements .....................................................................................4-794.12.1 Bridge Reset...........................................................................................................4-794.12.2 Configuring the PCI-to-PCI Bridge..........................................................................4-794.12.3 64-Bit Bus Configuration.........................................................................................4-804.13 Power-up/Default States..........................................................................................................4-81viDeveloper’s Manual