Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.16 ATU Interrupt Line Register - ATUILRATU Interrupt Line Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2.This register identifies the system interrupt controller's interrupt request lines which connect to thedevice's PCI interrupt request lines (as specified in the interrupt pin register).In a PC environment, for example, the register values and corresponding connections are:• 0 (00H) through 15 (0FH) correspond to IRQ0 through IRQ15• 16 (10H) through 254 (FEH) are reserved• 255 (FFH) indicates “unknown” or “no connection”The operating system or device driver can examine each device’s interrupt pin and interrupt lineregister to determine which system interrupt request line the device uses to issue requests forservice.Table 5-44.ATU Interrupt Line Register - ATUILRIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrw rw rw rw rw rw rw rwIntel ® 80200 Processor Local Bus Address123CHPCI Configuration Address Offset3CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:00 FFHInterrupt Assigned - system-assigned value identifies which system interrupt controller’s interruptrequest line connects to the device's PCI interrupt request lines (as specified in the interrupt pinregister).A value of FFH signifies “no connection” or “unknown”.Developer’s Manual 5-77