Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-23.PCI-to-PCI Bridge Register TableInternal BusAddressSection, Register Name - Acronym (Page)1000H Section 4.15.1, “Vendor Identification Register - VIDR” on page 4-851002H Section 4.15.2, “Device ID Register - DIDR” on page 4-861004H Section 4.15.3, “Primary Command Register - PCR” on page 4-871006H Section 4.15.4, “PrimaryStatusRegister-PSR” on page 4-881008H Section 4.15.5, “Revision ID Register - RID” on page 4-901009H Section 4.15.6, “Class Code Register - CCR” on page 4-91100CH Section 4.15.7, “Cacheline Size Register - CLSR” on page 4-92100DH Section 4.15.8, “Primary Latency Timer Register - PLTR” on page 4-93100EH Section 4.15.9, “HeaderTypeRegister-HTR” on page 4-941018H Section 4.15.10, “Primary Bus Number Register - PBNR” on page 4-951019H Section 4.15.11, “Secondary Bus Number Register - SBNR” on page 4-96101AH Section 4.15.12, “Subordinate Bus Number Register - SubBNR” on page 4-97101BH Section 4.15.13, “Secondary Latency Timer Register - SLTR” on page 4-98101CH Section 4.15.14, “I/O Base Register - IOBR” on page 4-99101DH Section 4.15.15, “I/O Limit Register - IOLR” on page 4-100101EH Section 4.15.16, “Secondary Status Register - SSR” on page 4-1011020H Section 4.15.17, “Memory Base Register - MBR” on page 4-1021022H Section 4.15.18, “Memory Limit Register - MLR” on page 4-1031024H Section 4.15.19, “Prefetchable Memory Base Register - PMBR” on page 4-1041026H Section 4.15.20, “Prefetchable Memory Limit Register - PMLR” on page 4-1051034H Section 4.15.21, “Capabilities Pointer Register - Cap_Ptr” on page 4-106103EH Section 4.15.22, “Bridge Control Register - BCR” on page 4-1071040H Section 4.15.23, “Extended Bridge Control Register - EBCR” on page 4-1091042H Section 4.15.24, “Secondary IDSEL Select Register - SISR” on page 4-1111044H Section 4.15.25, “Primary Bridge Interrupt Status Register - PBISR” on page 4-1131048H Section 4.15.26, “Secondary Bridge Interrupt Status Register - SBISR” on page 4-114104CH Section 4.15.27, “Secondary Arbitration Control Register - SACR” on page 4-1151050H Section 4.15.28, “PCI Interrupt Routing Select Register - PIRSR” on page 4-1151054H Section 4.15.29, “Secondary I/O Base Register - SIOBR” on page 4-1161055H Section 4.15.30, “Secondary I/O Limit Register - SIOLR” on page 4-1171056H Section 4.15.31, “Secondary Clock Disable Register - SCDR” on page 4-1181058H Section 4.15.32, “Secondary Memory Base Register - SMBR” on page 4-119105AH Section 4.15.33, “Secondary Memory Limit Register - SMLR” on page 4-120105CH Section 4.15.34, “Secondary Decode Enable Register - SDER” on page 4-121105EH Section 4.15.35, “Queue Control Register - QCR” on page 4-1231068H Section 4.15.36, “Capability Identifier Register - Cap_ID” on page 4-1241069H Section 4.15.37, “Next Item Pointer Register - Next_Item_Ptr” on page 4-125106AH Section 4.15.38, “Power Management Capabilities Register - PMCR” on page 4-126106CH Section 4.15.39, “Power Management Control/Status Register - PMCSR” on page 4-127106EH Section 4.15.40, “PMCSR PCI-to-PCI Bridge Support - PMCSR_BSE” on page 4-1284-84 Developer’s Manual