Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.19 Prefetchable Memory Base Register - PMBRThe Prefetchable Memory Base Register defines the bottom address (inclusive) of a prefetchablememory address range that is used to determine when to forward memory transactions from oneside of the bridge to the other. The Prefetchable Memory Base Register must be programmedbefore the Memory Space Enable bit of the Primary Command Register (PCR) is set. The upper12 bits correspond to AD[31:20] of 32-bit addresses. For the purposes of address decoding, thebridge assumes that AD[19:0], the lower 20 address bits of the memory base address, are zero.This means that the bottom of the defined address range will be aligned on a 1 Mbyte boundary.The VGA Enable bit in the BCR register forces the bridge to forward memory accesses in theaddress range from 0A0000H to 0BFFFFH from the Primary to Secondary and blocks addresses inthe same range from Secondary to Primary.Table 4-42.Prefetchable Memory Base Register - PMBRIOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rw rw rw rw rwrvrvrvrvPCI Configuration Offset24 - 25HIntel ® 80200 Processor Local Bus Address0000 1024HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:04 000HPrefetchable Memory Base Address - This field is programmed with AD[31:20] of the bottom of thememory address range to be passed down the hierarchy by the bridge.03:00 0H Reserved.4-104 Developer’s Manual