Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.5.1 I/O Address SpaceThe PCI-to-PCI bridge unit implements one programmable address range for PCI I/O transactions.A continuous I/O address space is defined by the I/O Base Register (IOBR) and the I/O LimitRegister (IOLR) in the bridge configuration space. The upper four bits of the IOBR correspond toAD[15:12] of the I/O address and the lower twelve bits are always 000H forcing a 4 Kbytealignment for the I/O address space. The upper four bits of the IOLR also correspond to AD[15:12]and the lower twelve bits are FFFH forcing a granularity of 4 Kbytes.The bridge unit will forward from the Primary to Secondary interface an I/O transaction that has anaddress within the address range defined (inclusively) by the IOBR and the IOLR. In this instancethe Primary interface acts as a PCI target and the Secondary interface acts as a PCI initiator for thebridged I/O transaction.When an I/O read or write transaction is present on the Secondary bus, the bridge unit forwards itto the Primary interface when the address is outside the address range defined by IOBR and IOLR.In this instance the Secondary interface acts as a PCI target and the Primary interface serves as aPCI initiator.The Intel ® 80312 I/O companion chip only supports 16-bit addresses for I/O transactions andtherefore any I/O transaction with an address greater than 64 Kbytes will not be forwarded overeither interface. The bridge assumes AD[31:16] = 0000H even though these bits are notimplemented in the IOBR and the IOLR. The bridge unit must still perform a full 32-bit decodeduring an I/O transaction to check for AD[31:16] = 0000H per the PCI Local Bus Specification,Revision 2.2.I/O Read and I/O Write transactions with invalid byte enables (those that are inconsistent with thebyte address) will be transparently passed by the bridge. In this case, it is expected that the targetwill target-abort, and the bridge will pass the target-abort back to the master.For all PCI I/O transactions (I/O Read/Write Commands), the bridge does not use the PCI 64-bitextensions. I/O cycles are performed as 32-bit transactions only (REQ64# is never asserted).The bridge response to I/O transactions can be modified by the following configuration bits:• Master Enable bit in the Primary Command Register (PCR)• I/O Enable bit in the Primary Command Register (PCR)• ISA Enable bit in the Bridge Control Register (BCR)• VGA Enable bit in the Bridge Control Register (BCRThe Master Enable bit needs to be set to allow the Primary interface to function as a PCI initiator(master) on behalf of transactions initiated on the Secondary bus. The I/O Enable bit must be set toallow the bridge to accept I/O transactions on the Primary interface. The VGA Enable bit in theBCR will cause I/O accesses where AD[9:0] are in the ranges 3B0H - 3BBH and 3C0H - 3DFH(inclusive of ISA addresses - AD[15:10] are not decoded) to be forwarded from primary tosecondary and blocked from secondary to primary. See Section 4.5.3, “VGA Address Support” onpage 4-20 for more details on VGA Compatible addressing.The ISA Enable bit is discussed in the following section.4-16 Developer’s Manual