Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip11-2 Duration Events .......................................................................................................................11-411-3 Relationship between the Monitored mode and Monitored Interface ......................................11-511-4 Event Monitor Register Table ................................................................................................11-2211-5 Global Timer Mode Register (GTMR)....................................................................................11-2311-6 Event Select Register (ESR) .................................................................................................11-2411-7 Event Monitoring Interrupt Status Register (EMISR).............................................................11-2511-8 Global Time Stamp Register - GTSR ....................................................................................11-2711-9 Programmable Event Counter Register - PECRx..................................................................11-2812-1 I 2 C Bus Definitions ..................................................................................................................12-212-2 Modes of Operation .................................................................................................................12-412-3 START and STOP Bit Definitions ............................................................................................12-512-4 ICCR Programming Values .....................................................................................................12-812-5 Master Transactions ..............................................................................................................12-1412-6 Slave Transactions ................................................................................................................12-1812-7 General Call Address Second Byte Definitions .....................................................................12-2112-8 I 2 C Register Summary Table.................................................................................................12-2612-9 I 2 C Control Register - ICR .....................................................................................................12-2712-10 I 2 C Status Register - ISR.......................................................................................................12-3012-11 I 2 C Slave Address Register - ISAR .......................................................................................12-3212-12 I 2 C Data Buffer Register - IDBR ............................................................................................12-3312-13 I 2 C Clock Count Register - ICCR ..........................................................................................12-3412-14 I 2 C Bus Monitor Register - IBMR...........................................................................................12-3513-1 GPIO Output Enable Register - GPOE....................................................................................13-213-2 GPIO Input Data Register - GPID............................................................................................13-413-3 Output Data Register - GPOD .................................................................................................13-514-1 TAP Controller Pin Definitions .................................................................................................14-214-2 Boundary-Scan Instruction Set................................................................................................14-314-3 IEEE Instructions .....................................................................................................................14-414-4 Intel ® 80312 I/O Companion Chip Boundary Scan Register Bit Order....................................14-615-1 Output Clocks Loading Summary............................................................................................15-315-2 Clock Pin Summary .................................................................................................................15-415-3 Intel ® 80312 I/O Companion Chip Clock Region Summary ....................................................15-415-4 Secondary PCI Bus Reset Summary ......................................................................................15-815-5 Internal Bus Reset Summary.................................................................................................15-1115-6 Reset Strap Signals...............................................................................................................15-1315-7 Reset Values .........................................................................................................................15-1415-8 Initialization Modes ................................................................................................................15-15A-1 Intel ® 80200 Processor Local Addresses Assigned to Integrated Peripherals......................... A-4A-2 Peripheral Memory-Mapped Register Locations ...................................................................... A-5xxviDeveloper’s Manual