Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11.2 Data Parity ErrorsWhen the bridge unit detects a data parity error, the bad data and bad parity will be passed to theopposite interface whenever possible. This will enable the parity error recovery mechanismsoutlined in the PCI Local Bus Specification, Revision 2.2 without special consideration for thebridge in the datapath.4.11.2.1 Read Data ParityWhen a data parity error is detected during a read transaction that crosses the bridge unit, it willassert PERR# on the target interface. The bridge will pass the bad data and the bad parity to theinitiating interface and bus where the initiator will also detect the bad parity and data and assertPERR# on the initiating bus. The bridge will set the Detected Parity Error bit and set the DataParity Detected bit (when enabled) in the PSR when the Primary interface is the target bus or theSSR when the Secondary interface is the target bus. When data parity is detected by the master onthe initiating bus, it will assert PERR#. No other action is taken by the bridge unit.Specifically for downstream reads (initiated by a master on the Primary bus interface), the Intel ®80312 I/O companion chip performs the following actions with the given constraints:• S_PERR# is asserted two clock cycles following the data phase in which the data parity erroris detected on the Secondary bus. This is only done when the Secondary Parity Error ResponseEnable bit in the Bridge Control Register (BCR) is set.• The Data Parity Detected bit in the Secondary Status Register (SSR) is set when the SecondaryParity Error Response Enable bit in the BCR is set. When the Secondary PCI Master ParityError Interrupt Mask bit in the SDER is clear, set the PCI Master Parity Error bit in the SBISR.• The Detected Parity Error bit in the SSR is set. When the Secondary Detected Parity ErrorInterrupt Mask bit is clear in the SDER, set the Detected Parity Error bit in the SBISR.• The data and the bad parity are stored in a DRC queue and returned to the master on thePrimary bus during Delayed Read Completion cycle. When the data word with the bad parityis not read from DRC queue by the initiator (i.e., delayed cycle read 32 bytes with an error inbyte 30 and the master only wanted 16 bytes) due to the prefetch algorithm (see Section 4.6.5),the data is discarded when the queue is invalidated and no other action is taken.Specifically for upstream reads (initiated by a master on the Secondary bus interface), the Intel ®80312 I/O companion chip performs the following actions with the given constraints:• P_PERR# is asserted two clocks cycles following the data phase in which the data parity erroris detected on the Primary bus. This is only done when the Primary Parity Error ResponseEnable bit in the Primary Command Register (PCR) is set.• The Data Parity Detected bit in the Primary Status Register (PSR) is set when the PrimaryParity Error Response Enable bit in the PCR is set. When the Primary PCI Master Parity ErrorInterrupt Mask bit in the SDER is clear, set the PCI Master Parity Error bit in the PBISR.• The Detected Parity Error bit in the PSR is set. When the Primary Detected Parity ErrorInterrupt Mask bit is clear in the SDER, set the Detected Parity Error bit in the PBISR.• The data and the bad parity are stored in a DRC queue and returned to the master on theSecondary bus during Delayed Read Completion cycle. When the data word with the badparity is not read from DRC queue by the initiator (i.e., delayed cycle read 32 bytes with anerror in byte 30 and the master only wanted 16 bytes) due to prefetch algorithm (seeSection 4.6.5), the data is discarded when the queue is invalidated and no other action is taken.In both cases, the initiator of the Delayed Read transaction is responsible for asserting PERR# onthe initiating bus (when enabled) in response to bridge unit delivering data along with the badparity.4-68 Developer’s Manual