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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Memory Controller3.6.2 SDRAM Control Register - SDCRThe SDRAM Control Register (SDCR) is responsible for programming the operation of theSDRAM state machines. The SDCR specifies the drive strength for the MCU pins, the bus width,and power failure handling. Refer to Table 3-19 for the recommended output buffer driveprogrammability.Table 3-18.SDRAM Control Register - SDCRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rw rw rw rv rv rvPCIAttributesnananananananananananananananananananananananananananananananana<strong>Intel</strong> ® 80200 Processor Local Bus Address1504HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:13 0 Reserved12:11 00 2SCAS#, SWE# SDRAM output buffers.Register can be programmed with four distinct drive strengths ranging from low to high:Address and Control Drive Strength: Controls the strength of the SA[12:0], SBA[1:0], SRAS#,(low drive strength) “00” => “01” => “10” => “11” (high drive strength)10:09 00 2 Register can be programmed with four distinct drive strengths ranging from low to high:Data Mask Drive Strength: Controls the strength of the SDQM[7:0] SDRAM output buffers.(low drive strength) “00” => “01” => “10” => “11” (high drive strength)08:07 00 2buffers.Register can be programmed with four distinct drive strengths ranging from low to high:<strong>Chip</strong> Enable 1 Drive Strength: Controls the strength of the SCE[1]# and SCKE[1] SDRAM output(low drive strength) “00” => “01” => “10” => “11” (high drive strength)06:05 00 2buffers.Register can be programmed with four distinct drive strengths ranging from low to high:<strong>Chip</strong> Enable 0 Drive Strength: Controls the strength of the SCE[0]# and SCKE[0] SDRAM output(low drive strength) “00” => “01” => “10” => “11” (high drive strength)04:03 00 2Data Bus Drive Strength: Controls the strength of the DQ[63:0] and SCB[7:0] SDRAM outputRegister can be programmed with four distinct drive strengths ranging from low to high:(low drive strength) “00” => “01” => “10” => “11” (high drive strength)02:00 000 2 Reserved03-46 Developer’s Manual

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