Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.12 Error ConditionsThere are four error conditions that may occur during a DMA transfer that are recorded by thechannel. All error conditions are reported by setting the appropriate bit in the Channel StatusRegister (CSR). The DMA controller must satisfy all “retries” even when an error condition occurson the opposite bus.The possible error conditions are:• PCI Master-Abort• PCI Target-Abort• PCI Data Parity Error• Internal Bus Errors9.12.1 PCI Errors• When a PCI Master-Abort occurs during a DMA transfer, the channel sets bit 3 in the CSR.The channel also reflects the error to the Address Translation Units (PATU or SATUdepending on which channel was the master while the error occurred). The ATU in turn,records this error condition by setting the appropriate bit in its status register (PATUSR orSATUSR). Refer to Chapter 4, “PCI-to-PCI Bridge Unit” for complete details.• When a PCI Target-Abort (Master) occurs during a DMA transfer, the channel sets bit 2 in theCSR. The channel also reflects the error to the Address Translation Units (PATU or SATUdepending on which channel was the master while the error occurred). The ATU in turn,records this error condition by setting the appropriate bit in its status register (PATUSR orSATUSR). Refer to Chapter 5, “PCI Address Translation Unit” for complete details.• When a PCI data parity error occurs during a DMA transfer, the channel sets bit 0 in the CSR.The channel also reflects the error to the Address Translation Units (PATU or SATUdepending on which channel was the master while the error occurred). The ATU in turn,records this error condition by setting the appropriate bit in its status register (PATUSR orSATUSR). For PCI parity errors, data with incorrect parity is never transferred to localmemory. Refer to Chapter 5, “PCI Address Translation Unit” for complete details.9.12.2 Internal Bus Errors• When an error occurs during a read of the Chain Descriptor or Next Descriptor Address, thechannel may set the Internal Bus Master-abort error flag in the CSR. Then, the channel loadsthe registers (when possible) and stop.• When an error occurs when the DMA channel is mastering a transaction on the PCI bus, thechannel prematurely ends the transaction and stop transferring data as soon as possible.• When the channel has asserted its PCI request signal, but not yet started the transaction, thechannel deasserts its request.• When the channel has not yet asserted a request for the PCI bus, the channel never asserts arequest for the bus.When an error condition occurs, the actions taken are detailed below:Developer’s Manual 9-23