Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.18 ATU Minimum Grant Register - ATUMGNTATU Minimum Grant Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2.This register specifies the burst period the device requires in increments of 8 PCI clocks.This register and the ATU Maximum Latency register are information-only registers which theconfiguration uses to determine how often a bus master typically requires access to the PCI bus andthe duration of a typical transfer when it does acquire the bus. This information is useful indetermining the values to be programmed into the bus master latency timers and in programmingthe algorithm to be used by the PCI bus arbiter.Table 5-46.ATU Minimum Grant Register - ATUMGNTIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrorororororororoIntel ® 80200 Processor Local Bus Address123EHPCI Configuration Address Offset3EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:00 00HThis register specifies how long a burst period the device needs in increments of 8 PCI clocks. A zerovalue indicates the device has no stringent requirement.Developer’s Manual 5-79