Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.3 Architectural DescriptionThe PCI-to-PCI bridge unit can be logically separated into four major components. They are:• Primary PCI Interface• Secondary PCI Interface• Upstream/Downstream Queues• Configuration Registers4.3.1 Primary PCI InterfaceThe Primary PCI interface of the PCI-to-PCI bridge unit can act either as a target or an initiator ofa PCI bus transaction. For most systems, the Primary interface will be connected to the PCI side ofa Host/PCI bridge which is typically the lowest numbered PCI bus in a system hierarchy. ThePrimary interface consists of the mandatory 50 signal pins defined within the PCI-to-PCI BridgeArchitecture Specification, Revision 1.1, four optional interrupt pins, one 66 MHz enable pin, andthe 39 pins required by the PCI 64-bit extension. Refer to the PCI Local Bus Specification,Revision 2.2 for a complete description of individual pin functionality.The Primary PCI interface implements both an initiator (master) and a target (slave) PCI device.When a PCI transaction is initiated on the Secondary bus, the Primary master state machinecompletes the transaction (write or read) as though it was the initiating device. The Primary PCIinterface, as a PCI target for transactions that need to complete on the Secondary bus, accepts thetransaction and forwards the request to the Secondary side. As a target, the Primary PCI interfaceuses positive decoding to claim the PCI transaction addressed below the bridge and then forwardthe transaction onto the Secondary master interface.The Primary PCI interface is responsible for all PCI command interpretation, address decoding anderror handling for transactions initiated on the PCI-to-PCI bridge Primary bus.The Primary interface of the Intel ® 80312 I/O companion chip supports enhanced PCI bandwidthof 528 MBytes/sec. through the use of the 64-bit PCI extension at a frequency of up to 66 MHz.The additional bandwidth that the Intel ® 80312 I/O companion chip Primary PCI interfaceprovides is used to support additional I/O bandwidth from the Secondary PCI bus as well asproviding a faster/wider pipe to the host processor memory bus.4.3.2 Secondary PCI InterfaceThe Secondary PCI interface of the PCI-to-PCI bridge unit functions in almost the same manner asthe Primary interface. It consists of both a PCI master and a PCI slave device and implements the“second” PCI bus with a new set of PCI electrical loads for use by the system. The Secondary PCIinterface consists of the mandatory 49 pins defined in the PCI-to-PCI Bridge ArchitectureSpecification, Revision 1.1, one 66 MHz enable pin, and the 39 pins required for the 64-bitextension. Four additional PCI interrupt pins are provided for use by Secondary PCI devices.As a slave (target), the Secondary PCI interface is responsible for claiming PCI transactions that donot fit within the bridge Secondary memory or I/O address space and forwarding them through thebridge to the addressed target on the Primary side. As a master (initiator), the Secondary PCI4-4 Developer’s Manual