Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.1.4 Inbound Configuration Cycle TranslationThe ATU only accepts Type 0 configuration cycles with a function number of one (the bridge isfunction0intheIntel ® 80312 I/O companion chip). (Refer to Section 5.2.4, “PCI Multi-FunctionDevice Swapping/Disabling” on page 5-24 for exceptions to this statement.)Both primary and secondary ATUs are configured through the primary ATU. This means that onlyone configuration space exists for both PCI buses. All inbound configuration cycles are processedas delayed transactions. The translation mechanism for inbound configuration cycles is defined bythe PCI Local Bus Specification, Revision 2.2.The ATU configuration space is selected by a PCI configuration command and claims the access(by asserting P_DEVSEL#) whentheP_IDSEL pin is asserted, the PCI command indicates aconfiguration read or write, and address bits P_AD[1:0] are 00 2 all during the address phase. TheATU primary interface ignores any configuration command (P_IDSEL active) where P_AD[1:0]are not 00 2 (e.g., Type 1 commands). During the configuration access address phase, the PCIaddress is divided into a number of fields to determine the actual configuration register access.These fields, in combination with the byte enables during the data phase create the unique encodingnecessary to access the individual registers of the configuration address space:• P_AD[7:2] - Register Number. Selects one of 64 DWORD registers in the ATU PCIconfiguration address space.• P_C/BE[3:0]# - Used during the data phase. Selects which actual configuration register isused within the DWORD address. Creates byte addressability of the register space.• P_AD[10:8] - Function Number. Used to select which function of a multi-function device isbeing accessed. The ATUs are function 1 and therefore it only responds to 001 2 in this bit fieldand ignore all other bit combinations. (Refer to Section 5.2.4, “PCI Multi-Function DeviceSwapping/Disabling” on page 5-24 for exceptions to this statement.)The ATU configuration address space starts at internal address 0000.1200H. Therefore P_AD[7:2]equal to 000000 2 equates to address 0000.1200H and P_AD[7:2] equal to 000001 2 results inaddress 0000.1204H and so on.For inbound configuration reads, the IRQ and ITQ are used in the same manner as inboundmemory read operations. The internal bus cycle that results is a 32-bit transaction. For inboundconfiguration writes, the PATU adds a delayed write data queue, IDWQ, which holds data in thesame manner as the IWQ. The transaction information from the configuration write operation onthe primary PCI interface is latched into the IDWQ (when full, a Retry is signaled). The data fromthe delayed write request cycle is latched into the IDWQ and forwarded to the internal businterface. Once transaction ordering and priority have been satisfied, the internal bus masterinterface requests the internal bus and deliver the write data to the target as defined inSection 5.2.1.2.The status of the transaction on the internal bus is returned to the PCI initiator on the primary PCIbus. The retry cycle from the initiator is accepted once the write has been completed on the internalbus and the status has been latched for return to the PCI master. Since Master Aborts and TargetAborts cannot occur during configuration cycles on the internal bus, normal completion status isreturned. The data from PCI completion transaction is discarded.Developer’s Manual 5-13