Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.5 Default StatusThe interrupt logic is reset by the primary PCI reset signal or through software. Table 2-6 showsthe power-up and reset values.Table 2-6.Default Interrupt Routing and Status ValuesRegister Default Value DescriptionPIRSR000000HAll interrupts IRQ[3:0] routed to theFIQ# output pin.IRQ Interrupt Latch 0000 00000 2 All interrupts clearedFIQ2 Interrupt Latch 00000 2 All interrupts clearedFIQ1 Interrupt Latch 00H All interrupts clearedIRQ Interrupt Status Register 0000 0000H No interrupts setFIQ2 Interrupt Status Register 0000 0000H No interrupts setFIQ1 Interrupt Status Register 0000 0000H No interrupts set2.6 Performance RequirementsThe interrupt routing logic shall accept the routing control value written to the PIRSR register andaccept the changes within one clock after the write has completed. When the processor reads thePIRSR register, the value shall be returned immediately, effectively zero wait states.When the processor reads the IRQISR, FIQ1ISR and FIQ2ISR registers, the value shall be returnedimmediately, effectively zero wait states.The logic shall introduce no more than one clock delay when the interrupt is recognized on theinput of the logic until the signal is driven either to the Intel ® 80200 processor or the PCI outputinterrupt pins.Developer’s Manual 2-9