Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.6 Index RegistersThe Index Registers are a set of 1004 registers that, when written by an external PCI agent, cangenerate an interrupt to the Intel ® 80200 processor. These registers are for inbound messages only.The interrupt is recorded in the Inbound Interrupt Status Register.The storage for the Index Registers is allocated from the Intel ® 80200 processor local memory. PCIwrite accesses to the Index Registers write the data to local memory. PCI read accesses to the IndexRegisters read the data from local memory. The local memory used for the Index Registers rangesfrom Primary Inbound ATU Translate Value Register + 050H to Primary Inbound ATU TranslateValue Register + FFFH. Chapter 5, “PCI Address Translation Unit” describes how PCI addressesare translated to local memory addresses.The address of the first write access is stored in the Index Address Register. This register is writtenduring the earliest write access and provides a means to determine which Index Register waswritten. Once updated by the MU, the Index Address Register is not updated until the IndexRegister Interrupt bit in the Inbound Interrupt Status Register is cleared. When the interrupt iscleared, the Index Address Register is re-enabled and stores the address of the next Index Registerwrite access.Writes by the Intel ® 80200 processor to the local memory used by the Index Registers does notcause an interrupt and does not update the Index Address Register.The index registers can be accessed with multi-word reads and single quad-word aligned writes.6.7 Messaging Unit Error ConditionsThe Messaging Unit, like the Primary ATU, encounters error conditions on the PCI interface aswell as the internal bus interface. As a PCI target, all PCI errors (parity and aborts) are capturedand recorded in the Primary ATU Status Register and can be masked using the PATU mechanisms.Refer to Chapter 5, “PCI Address Translation Unit” for further details.Developer’s Manual 6-15