Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.5.6 Private Address SpaceThe bridge supports private address space by not claiming and forwarding upstream privateMemory and I/O addresses on the Secondary PCI bus. These private addresses will appear to thebridge as Primary PCI addresses because they fall outside the Secondary PCI address space.Private addresses are only supported on the Secondary PCI bus and may be used for transactionsfrom private devices to the Secondary ATU, transactions from the Intel ® 80312 I/O companionchip to private devices, or transactions from private device to private device. The bridge will notclaim transactions with these three types of private addresses when private addressing has beenenabled:1. Inbound transactions from private devices to the Secondary ATU.2. Outbound transactions from the Secondary ATU or DMA channel 2 to private devices.3. Peer transactions from Secondary devices.For inbound private transactions, the Secondary ATU is responsible for claiming thesetransactions. When the Secondary ATU claims the transaction, the bridge will not claim or try toforward the transaction. The inbound ATU address space takes precedence over the inversedecoding performed by the bridge on the Secondary PCI interface.For outbound transactions from the Secondary ATU or DMA channel 2, or peer transactions fromSecondary device to private device, the programmer must use the Secondary Memory BaseRegister and Secondary Memory Limit Register (SMBR/SMLR) to define a private memoryaddress range and the Secondary I/O Base Register and the Secondary I/O Limit Register(SIOBR/SIOLR) to define a private I/O address range. To enable this feature, the Private MemorySpace Enable bit in the Secondary Decode Enable Register must be set. See Section 4.15.34. Thebridge will not claim any Secondary PCI address that falls within a valid SMBR/SMLR andSIOBR/SIOLR address ranges when the Private Memory Space Enable or the Private I/O SpaceEnable bits are set.4.5.7 Secondary PCI to Messaging Unit AccessThe PCI-to-PCI bridge unit is responsible for providing the data path for access to the MessagingUnit (part of the Primary ATU). The bridge, in conjunction with the SATU, allows Secondary PCImasters to read and write the first 4 KB of the PATU inbound address space (the MU). Thefollowing statements apply to accessing the MU from the Secondary PCI bus through the bridge:• The Secondary Bus - Messaging Unit Access Enable bit must be set. When set, the SATU willnot claim the first 4 KB of its inbound address space, allowing the bridge the opportunity. Thisbit is contained in the ATUCR in the ATU configuration space (see Chapter5,“PCIAddressTranslation Unit”).• The PCI memory read or write transaction (I/O or configuration cycles are not supported) musthave a valid bridge address outside the PMBR/PMLR and MBR/MLR address ranges.• The bridge unit Primary interface takes no other action to allow Secondary access to the MU.The application programmer is responsible for guaranteeing that the MU address is accessiblefrom the Secondary PCI interface as an upstream bridge transaction. When the upstreamtransaction, meant for the Messaging Unit, is not at the correct address, a master abort willoccur or the transaction will be claimed by the incorrect target.• Normal Upstream read prefetch behavior applies. The Messaging Unit will disconnect (as a32-bit device) after delivering one 32-bit Dword.4-24 Developer’s Manual