Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitThe data flow for an outbound read transaction on the PCI bus is summarized in the followingstatements:• The ATU PCI interface requests the PCI bus when an address is written to the OTQ (a readrequest). Once the bus is granted, the PCI interface transfers the PCI translated address fromthe OTQ to the PCI bus and wait for the transaction to be claimed.• If no DEVSEL# is asserted, a master abort is signaled. This is passed through to the internalbus slave interface.• Once the transaction is claimed and data is provided by the target, the PCI interface continuereading until the fetch data amount is satisfied. The master interface stops reading under thefollowing circumstances:— A disconnect is signaled from the PCI target. The master interface attempts to reacquirethe bus and continue reading until the fetch data size is satisfied.— The master interface loses GNT# and the interface MLT has expired. A mastercompletion is performed and the interface attempts to reacquire the bus and continuesreading until the fetch data size is satisfied.— A target abort is signaled from the PCI target. The target abort is returned to the internalbus and the PCI interface returns to idle. The appropriate error bits are set as defined inSection 5.6.4.— The fetch data size has been reached. The master interface performs a master completionand the interface returns to idle.If the PCI target inserts waitstates at any point, the PCI master interface halts untilTRDY# is asserted. No other action is taken.5-22 Developer’s Manual