Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.8.5 I 2 C Clock Count Register- ICCRThe I 2 C Clock Count Register (ICCR) defines the multiplier used to generate the I 2 C SCL clock.This register is used with an internal 9-bit counter. When the SCL enable bit in the ICR is set, thiscounter decrements from the programmed ICCR value to zero, then resets to the programmedICCR value and decrements again. This continues until the SCL enable bit in the ICR is cleared.Each time the counter reaches zero, the SCL line transitions from low to high or vice versa,depending on the current state. This creates the I 2 C clock output during I 2 C master operations.Changing this register while the SCL enable bit is set results in undefined behavior.Table 12-13.I 2 C Clock Count Register - ICCRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1690HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:10 000000H Reserved09:00 0I 2 C Clock Count: 9 bit count value used to generate an I 2 C clock from the Intel ® 80312 I/O companionchip internal bus clock.12-34 Developer’s Manual
Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.8.6 I 2 C Bus Monitor Register- IBMRThe I 2 C Bus Monitor Register (IBMR) tracks the status of the SCL and SDA pins. The values ofthese pins are recorded in this read-only register so that software may determine when the I 2 Cbusis hung and the I 2 C unit must be reset.Table 12-14.I 2 C Bus Monitor Register - IBMRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro roPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1694HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:02 0 Reserved01 1 SCL Status: This bit continuously reflects the value of the SCL pin.00 1 SDA Status: This bit continuously reflects the value of the SDA pin.Developer’s Manual 12-35
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Memory Controller 3This chapter des
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