Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.7 Data AlignmentEach channel contains a hardware data alignment unit to support unaligned data transfers betweenthe source and destination busses. The data alignment unit optimizes data transfers to and from32- and 64-bit memory. The channel reformats data words for the correct bus data width.Aligned data transfers involve data accesses that fall on natural boundaries. For example; doublewords are aligned on 8-byte boundaries and words are aligned on 4-byte boundaries. DMAtransfers can occur with both the source and destination addresses unaligned.9.7.1 64-bit Unaligned Data TransfersFigure 9-7 illustrates a DMA transfer between unaligned 64-bit source and destination addresses.Figure 9-7.Optimization of an Unaligned DMAMSBMemoryLSBADDRESS64-bit Source bus(PCI Bus)7 6 5 4 3 2 115 14 13 12 11 10 9 820 19 18 17 16A000 0200HA000 0208HA000 0210HREQ64#. andACK64# sampledassertedDestination bus(internal bus)19 8 7 6 5 4 3 24001 0300H4001 0308H17 16 15 14 13 12 11 104001 0310H20 19 18 4001 0318HCCRPADRProgrammed Values0000 0001HA000 0201H10byte numberBus operationPUADRLADRBCR0000 0000H4001 0307H0000 0014HSOURCEdouble word load@ A0000200double word load@ A0000208double word load@ A0000210DESTINATIONbyte store@ 40010307double word store@ 40010308double word store@ 400103103-byte store@ 40010318DCR0000 0006HDeveloper’s Manual 9-17