Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.3 Hardware-Assist XOR UnitThe Application Accelerator Unit implements the XOR algorithm in hardware. It performs theXOR operation on multiple blocks of source (incoming) data and stores the result back in Intel ®80200 processor local memory.• The process of reading source data, executing the XOR algorithm, and storing the XOR datahereafter is referred to as XOR-transfer.• The process of reading or writing data hereafter is referred to as data transfer.The source and destination addresses are specified through chain descriptors resident in Intel ®80200 processor local memory.10.3.1 Data TransferAll transfers are configured and initiated through a set of memory-mapped registers and one ormore chain descriptors located in local memory. A transfer is defined by the source address,destination address, number of bytes to transfer, and control values. These values are loaded in thechain descriptor before a transfer begins. Table 10-1 describes the registers that need to beconfigured for any operation.Table 10-1.Register DescriptionRegister Abbreviation DescriptionAccelerator Control Register ACR Application Accelerator Control WordAccelerator Status Register ASR Application Accelerator Status WordAccelerator Descriptor Address Register ADAR Address of Current Chain DescriptorAccelerator Next Descriptor AddressRegisterANDARAddress of Next Chain DescriptorSource Address Register SAR1.. SAR8 Local memory addresses of source dataDestination Address Register DAR Local memory address of destination dataAccelerator Byte Count Register ABCR Number of Bytes to transferAccelerator Descriptor Control Register ADCR Chain Descriptor Control WordDeveloper’s Manual 10-3