Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.4 Expansion ROM Translation UnitThe primary inbound ATU supports one address range (defined by a base/limit register pair) usedfor the Expansion ROM. Refer to the PCI Local Bus Specification, Revision 2.2 for details onExpansion ROM format and usage.During a powerup sequence, initialization code from Expansion ROM is executed once by the hostprocessor to initialize the associated device. The code can be discarded once executed. ExpansionROM registers are described inSection 5.7.13, Section 5.7.31, andSection 5.7.32.The inbound primary ATU supports an inbound Expansion ROM window which works like theinbound translation window. A read from the expansion ROM windows is forwarded to the internalbus and to the Memory Controller. The address translation algorithm is the same as the inboundtranslation; see Section 5.2.1.1, “Inbound Address Translation” on page 5-6. The only widthExpansion ROM supported by the Intel ® 80312 I/O companion chip Memory Controller is an 8-bitnon-volatile device (FLASH/EPROM/ROM). The PATU uses standard 64-bit accesses on theinternal bus and the responsibility for packing the data from the 8-bit device resides with theMemory Controller.The Expansion ROM unit uses the primary ATU inbound transaction queue and the inbound readdata queue. The address of the inbound delayed read cycle is entered into the P_ITQx queue andthe delayed read completion data is returned in the P_IRQ. Expansion ROM writes are notsupported and result in a Target Abort. The internal bus master interface fills the P_IRQ read queuewith a minimum of 8-bytes in response to a read on the PCI bus. As a PCI target, the ExpansionROM interface behaves as a standard ATU interface and is capable of returning a 64-byte access bythe assertion of P_ACK64# in response to a 64-bit request.Developer’s Manual 5-31