Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.3 Primary Command Register - PCRPrimary Command Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2 and in most cases affect the behavior of the Primary interface of the PCI-to-PCIbridge.Table 4-26.Primary Command Register - PCRIOPAttributes15 12 8 4 0rv rv rv rv rv rv ro rw ro rw rv ro ro rw rw rwPCIAttributesrvrvrvrvrvrvrorwrorwrvrororw rw rwPCI Configuration Offset04 - 05HIntel ® 80200 Processor Local Bus Address0000 1004HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:10 00000 2 Reserved.09 0 2 Fast Back to Back Enable - This Primary interface does not perform fast back to back transactions.SERR# Enable - When this bit is cleared, the Intel08 0 ® 80312 I/O companion chip is not allowed to assert2 P_SERR# on its Primary interface.07 0 2 Wait Cycle Control - controls address/data stepping. Not implemented and a reserved bit fieldPrimary Parity Error Response Enable - When this bit is set, then the bridge must take normal action06 0 2 when a parity error is detected. When it is cleared, then parity checking is disabled.05 0 2 VGA Palette Snoop Enable - VGA Palette Snooping is not supported.04 0 2Memory Write and Invalidate Enable - Not applicable. A PCI-to-PCI bridge does not initiate MWIcommands, only forwards them on behalf of another master. The initiator has the control to determinewhichtypeofwritecommandtouse.Special Cycle Enable - The bridge cannot respond as the target of a Special Cycle so this bit field is03 0 2 defined as read only.02 0 2Bus Master Enable - Controls the bridge ability to operate as a master on the Primary interface formemory and I/O transactions. This bit does not affect the bridge ability to forward or convert Type 1configuration commands. When this bit is set, the bridge is enabled to act as a master on the Primaryinterface. When this bit is clear, the bridge will not claim any memory or I/O transactions on theSecondary PCI interface.Memory Enable - Controls the bridge response to both memory and prefetchable memory accesses.01 0 2 When this bit is cleared, the bridge will not respond to any memory access on the Primary PCI interface.I/O Space Enable - Controls the bridges response to I/O transactions on the Primary PCI interface.00 0 2 When this bit is cleared, the bridge will not respond to any I/O transaction on the Primary side.Developer’s Manual 4-87