Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory ControllerFigure 3-22 illustrates the SDRAM waveforms upon the assertion of I_RST#.Figure 3-22.Power Failure SequenceDCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15I_RST#SCE[0]#SCE[1]#SRAS#SCAS#SWE#SA[10]SCKE[0]SCKE[1]Resetdue to Power FailWait for 8 to 10 clocksPrecharge-AllT rp16 17 18 19Auto-RefreshT rcSelf-Refresh20SCKE[1:0] must be held low throughout the power-down period. The memory controller drives itlow initially with the self-refresh command, but an external pull-down is required to continuallydriveitlowwhentheIntel ® 80312 I/O companion chip loses power. External logic ensures thatSCKE[1:0] is held low after the memory controller initially deasserts it. Likewise, the externallogic must stop driving SCKE[1:0] low once P_RST# is deasserted by the system. Figure 3-23shows one example of the external logic required for power failure mode.As long as the SDRAM memory subsystem is powered with a battery source and SCKE[1:0] isheld low, the SDRAM preserves its memory image.When power is restored, the system asserts P_RST# to the Intel ® 80312 I/O companion chip.While the Intel ® 80312 I/O companion chip is reset, SCKE[1:0] is held low by the memorycontroller. After P_RST# is deasserted (and subsequently, I_RST# is deasserted), the Intel ® 80312I/O companion chip must be re-initialized to reset the CAS Latency parameter. The MRS commandissued to the SDRAM subsystem re-asserts SCKE[1:0] to ones and the memory controller resumesrefreshing. The SDRAM initialization sequence does not affect the memory contents. For moredetails about the SDRAM initialization sequence, refer to Section 3.2.3.5, “SDRAM Initialization”on page 3-19.Note:The power failure mechanism in the memory controller is not responsible for maintaining theIntel ® 80312 I/O companion chip state. The purpose of this mechanism is to maintain the memoryso that any data cached in the local memory can be flushed once power is restored. Any dataqueued within the Intel ® 80312 I/O companion chip’s components (ATUs, CIU, etc.) is lost.3-38 Developer’s Manual