Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitWhen the I 2 C Bus Interface Unit receives an address that matches the 7-bit address found in theI 2 C Slave Address Register (ISAR) or the General Call Address (00H), the interface either remainsin Slave-Receive mode or transitions to Slave-Transmit mode. This is determined by theRead/Write (R/W#) bit (the least significant bit of the byte containing the slave address). When theR/W# bit is low, the master initiating the transaction intends to do a write and the I 2 C Bus InterfaceUnit remains in Slave-Receive mode. When the R/W# is high, the initiating master wants to readdata and the slave transitions to Slave-Transmit mode. Slave operation is further defined inSection 12.3.6, “Slave Operations” on page 12-18.When the Intel ® 80200 processor wants to initiate a read or write on the I 2 C bus, the I 2 CBusInterface Unit transitions from the default Slave-Receive mode to Master-Transmit mode. Whenthe Intel ® 80200 processor wants to write data, the interface remains in Master-Transmit modeafter the address transfer has completed. (see Section 12.2.3.1, “START Condition” on page 12-6)for START information). When the Intel ® 80200 processor wants to read data, the I 2 CBusInterface Unit transmits the start address, then transition to Master-Receive mode. Master operationis further defined in Section 12.3.5, “Master Operations” on page 12-14.12.2.3 Start and Stop Bus StatesThe I 2 C bus defines a transaction START and a transaction STOP bus state that are used at thebeginning and end of the transfer of one to an unlimited number of bytes on the bus.The Intel ® 80312 I/O companion chip uses the START and STOP bits in the I 2 C Control Register(ICR) to:• initiate an additional byte transfer• initiate a START condition on the I 2 C bus• enable Data Chaining (repeated START)• initiate a STOP condition on the I 2 C busTable 12-3 summarizes the definition of the START and STOP bits in the ICR.Table 12-3.START and STOP Bit DefinitionsSTOPbitSTARTbitConditionNotes0 00 1No START orSTOPSTARTCondition andRepeatedSTART• No START or STOP condition is sent by the I 2 C Bus Interface Unit.This is used when multiple data bytes need to be transferred.• I 2 C Bus Interface Unit sends a START condition and transmit thecontents of the 8 bit IDBR after the START. The IDBR must containthe 7-bit address and the R/W# bit before a START is initiated.• For a repeated start, the IDBR contents contains the target slaveaddress and the R/W# bit. This enables multiple transfers to differentslaves without giving up the bus.• The interface stays in Master-Transmit mode when a write is used ortransition to master-receive mode when a read is requested.1 X STOP Condition• In Master-Transmit mode, the I 2 C Bus Interface Unit transmits the8-bit IDBR and then send a STOP on the I 2 Cbus.• In Master-Receive mode, the Ack/Nack Control bit in the ICR mustbe changed to a negative Ack (see Section 12.3.3). The I 2 CBusInterface Unit writes the Nack bit (Ack/Nack Control bit must be 1),receive the data byte in the IDBR, then send a STOP on the I 2 Cbus.Developer’s Manual 12-5