Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.5.3 VGA Address SupportOf the issues related to the use of VGA compatible devices in systems with Intel ® 80312 I/Ocompanion chip devices are VGA-ISA compatible addressing and VGA palette snooping. Tosupport a VGA device on a downstream bus from the Intel ® 80312 I/O companion chip, thePCI-to-PCI bridge is able to recognize and forward VGA addresses on the Primary interface to theSecondary interface. The PCI-to-PCI bridge unit of the Intel ® 80312 I/O companion chip devicedoes not support VGA palette snooping.4.5.3.1 VGA Compatible AddressingVGA addressing is used to allow the PCI-to-PCI bridge to support VGA frame buffer addressingand VGA register addressing. When the VGA Enable bit is set in the Bridge Command Register,the PCI-to-PCI bridge will positively decode memory accesses to a VGA frame buffer and I/Oaccesses to VGA registers on a Secondary bus. The following addresses are positively decoded onthe Primary interface when the VGA Enable bit is set:• VGA memory accesses - 0A0000H - 0BFFFFH• VGA I/O accesses - AD[9:0] = 3B0H - 3BBH and 3C0H - 3DFH. These addresses areinclusive of ISA aliasing since AD[15:10] are not decoded for VGA I/O accesses These I/Oaddresses are aliased every 1KB throughout the first 64KB of I/O space. This means thatAD[31:16] = 0000H.VGA compatible addressing, when the VGA Enable bit is set, is not dependent on the addressranges programmed into the MBR/MLR and PMBR/PMLR register pairs for memory or theIOBR/IOLR register pair. The stated addresses will be forwarded from primary to secondary andblocked from secondary to primary regardless of the defined address ranges. In addition, VGAcompatible addressing is not dependent on the ISA enable bit. VGA compatible addressing isdependent upon the I/O Enable bit and the Memory Enable bit and the respective memory and I/Otransactions will be disabled when the appropriate I/O and memory bits are not set.Figure 4-7.VGA Compatible AddressingPrimary Secondary Primary Secondary0A 0000H0B FFFFH3B0H-3BBH3C0H-3DFH7B0H-7BBHMemory BaseAddress RangePrefetchableMemory BaseAddress Range7C0H-7DFHBB0H-BBBHBC0H-BDFH....I/O BaseAddress RangeVGA Memory DecodingVGA I/O Decoding4-20 Developer’s Manual